NQ80331M667SL7NM Intel, NQ80331M667SL7NM Datasheet - Page 21

• Manufacturer Part Number: NQ80331M667SL7NM
• Description: IC I/O PROCESSOR 733MHZ 829-BGA
• Manufacturer: Intel

Specifications of NQ80331M667SL7NM

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 1.35V
• Mounting Type: Surface Mount
• Package / Case: 829-BGA
• Other names: 862506

Document Number: 273943-002
Table 7.
Secondary PCI Bus Signals (Sheet 1 of 2)
S_C/BE[3:0]#
S_C/BE[7:4]#
S_AD[63:32]
S_DEVSEL#
S_AD[31:0]
S_FRAME#
S_REQ64#
S_ACK64#
S_SERR#
S_TRDY#
S_STOP#
S_PAR64
S_IRDY#
S_RST#
S_PAR
Name
Count
32
32
1
1
4
4
1
1
1
1
1
1
1
1
1
Sync(S)
Sync(S)
Sync(S)
Sync(S)
Sync(S)
Sync(S)
Sync(S)
Sync(S)
Sync(S)
Sync(S)
Sync(S)
Sync(S)
Sync(S)
Sync(S)
Rst(S)
Rst(S)
Rst(S)
Rst(S)
Rst(S)
Rst(S)
Rst(S)
Rst(S)
Rst(S)
Rst(S)
Rst(S)
Rst(S)
Rst(S)
Rst(S)
Async
Type
November 2004
OD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Secondary PCI Address/Data is the multiplexed PCI address
and lower 32 bits of the data bus.
Secondary PCI Address/Data is the upper 32 bits of the PCI data
bus.
Secondary PCI Bus Parity is even parity across S_AD[31:0] and
S_C/BE[3:0]#.
Secondary PCI Bus Upper DWORD Parity is even parity across
S_AD[63:32] and S_C/BE[7:4]#.
Secondary PCI Bus Command and Byte Enables are
multiplexed on the same PCI pins. During the address phase, they
define the bus command. During the data phase, they are used as
the byte enables for S_AD[31:0].
Secondary PCI Byte Enables are used as byte enables for
S_AD[63:32] during secondary PCI data phases.
Secondary PCI Bus Request 64-Bit Transfer indicates the
attempt of a 64-bit transaction on the secondary PCI bus. When
the target is 64-bit capable, the target acknowledges the attempt
with the assertion of S_ACK64#.
Secondary PCI Bus Acknowledge 64-Bit Transfer indicates the
device has positively decoded its address as the target of the current
access, indicates the target is willing to transfer data using 64 bits.
Secondary PCI Bus Cycle Frame is asserted to indicate the
beginning and duration of an access.
Secondary PCI Bus Initiator Ready indicates the initiating agent
ability to complete current data phase of transaction. During a write, it
indicates valid data is present on the secondary Address/Data bus.
During a read, it indicates the processor is ready to accept the data.
Secondary PCI Bus Target Ready indicates the target agent ability
to complete the current data phase of the transaction. During a read,
it indicates that valid data is present on the secondary Address/Data
bus. During a write, it indicates the target is ready to accept the data.
Secondary PCI Bus Stop indicates a request to stop the current
transaction on the secondary PCI bus.
Secondary PCI Bus Device Select is driven by a target agent
that has successfully decoded the address. As an input, it
indicates whether or not an agent has been selected.
Secondary PCI Bus System Error is driven for address parity
errors on the secondary PCI bus.
Secondary PCI Bus Reset is an output based on P_RST#. It brings
PCI-specific registers, sequencers, and signals to a consistent state.
When P_RST# is asserted, it causes S_RST# to assert and:
S_RST# may be asynchronous to S_CLKIN when asserted or
deasserted. Although asynchronous, deassertion must be
ensured to be a clean, bounce-free edge.
• PCI output signals are driven to a known consistent state.
• PCI bus interface output signals are three-stated.
• Open drain signals such as S_SERR# are floated.
Intel® 80331 I/O Processor Datasheet
Description
Package Information
21