CY7C63923-PVXC Cypress Semiconductor Corp, CY7C63923-PVXC Datasheet - Page 8
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CY7C63923-PVXC
Manufacturer Part Number
CY7C63923-PVXC
Description
IC USB PERIPHERAL CTRLR 48-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet
1.CY7C63823-PXC.pdf
(68 pages)
Specifications of CY7C63923-PVXC
Controller Type
USB Peripheral Controller
Interface
USB
Voltage - Supply
4 V ~ 5.5 V
Current - Supply
40mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C63923-PVXC
Manufacturer:
CY
Quantity:
14
Part Number:
CY7C63923-PVXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document 38-08035 Rev. *E
7.0
7.1
The Flags Register can only be set or reset with logical
instruction.
Table 7-1. CPU Flags Register (CPU_F) [R/W]
7.1.1
Table 7-2. CPU Accumulator Register (CPU_A)
7.1.2
Table 7-3. CPU X Register (CPU_X)
Bit [7:5]: Reserved
Bit 4: XIO
Set by the user to select between the register banks
0 = Bank 0
1 = Bank 1
Bit 3: Super
Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user)
0 = User Code
1 = Supervisor Code
Bit 2: Carry
Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation
0 = No Carry
1 = Carry
Bit 1: Zero
Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation
0 = Not Equal to Zero
1 = Equal to Zero
Bit 0: Global IE
Determines whether all interrupts are enabled or disabled
0 = Disabled
1 = Enabled
Note: CPU_F register is only readable with explicit register address 0xF7. The OR F, expr and AND F, expr instructions must
be used to set and clear the CPU_F bits
Bit [7:0]: CPU Accumulator [7:0]
8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode
Bit [7:0]: X [7:0]
8-bit data value holds an index for any instruction that uses an indexed addressing mode
Read/Write
Read/Write
Read/Write
Default
Default
Default
Field
Field
Field
Bit #
Bit #
Bit #
Flags Register
Accumulator Register
Index Register
CPU Registers
7
–
0
7
–
0
7
–
0
Reserved
6
–
0
6
–
0
6
–
0
5
–
0
5
–
0
5
–
0
CPU Accumulator [7:0]
R/W
XIO
4
0
4
–
0
4
–
0
X [7:0]
Super
R
3
0
3
–
0
3
–
0
Carry
RW
2
0
2
–
0
2
–
0
Zero
RW
1
1
1
–
0
1
–
0
CY7C63310
CY7C638xx
CY7C639xx
Page 8 of 68
Global IE
RW
0
0
0
–
0
0
–
0