CY7C63923-PVXC Cypress Semiconductor Corp, CY7C63923-PVXC Datasheet - Page 40

• Manufacturer Part Number: CY7C63923-PVXC
• Description: IC USB PERIPHERAL CTRLR 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63923-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Document 38-08035 Rev. *E
16.1.11 Timer Configuration
Table 16-11. Timer Configuration (TMRCR) [0x2A] [R/W]
16.1.12 Capture Interrupt Enable
Table 16-12. Capture Interrupt Enable (TCAPINTE) [0x2B] [R/W]
Bit 7: First Edge Hold
The First Edge Hold function applies to all four capture timers.
0 = The time of the most recent edge is held in the Capture Timer Data Register. If multiple edges have occurred since reading
the capture timer, the time for the most recent one will be read
1 = The time of the first occurrence of an edge is held in the Capture Timer Data Register until the data is read. Subsequent
edges are ignored until the Capture Timer Data Register is read.
Bit [6:4]: 8-bit Capture Prescale [2:0]
This field controls which 8 bits of the 16 Free Running Timer are captured when in bit mode
0 0 0 = capture timer[7:0]
0 0 1 = capture timer[8:1]
0 1 0 = capture timer[9:2]
0 1 1 = capture timer[10:3]
1 0 0 = capture timer[11:4]
1 0 1 = capture timer[12:5]
1 1 0 = capture timer[13:6]
1 1 1 = capture timer[14:7]
Bit 3: Cap0 16-bit Enable
0 = Capture 0 16-bit mode is disabled
1 = Capture 0 16-bit mode is enabled. Capture 1 is disabled and the Capture 1 rising and falling registers are used as an extension
to the Capture 0 registers—extending them to 16 bits
Bit [2:0]: Reserved
Bit [7:4]: Reserved
Bit 3: Cap1 Fall Enable
0 = Disable the capture 1 falling edge interrupt
1 = Enable the capture 1 falling edge interrupt
Bit 2: Cap1 Rise Enable
0 = Disable the capture 1 rising edge interrupt
1 = Enable the capture 1 rising edge interrupt
Bit 1: Cap0 Fall Enable
0 = Disable the capture 0 falling edge interrupt
1 = Enable the capture 0 falling edge interrupt
Bit 0: Cap0 Rise Enable
0 = Disable the capture 0 rising edge interrupt
1 = Enable the capture 0 rising edge interrupt
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
First Edge Hold
R/W
7
0
7
–
0
R/W
6
0
6
–
0
Reserved
8-bit Capture Prescale [2:0]
R/W
5
0
5
–
0
R/W
4
0
4
–
0
Cap0 16bit
Cap1 Fall
Enable
Enable
R/W
R/W
3
0
3
0
Cap1 Rise
Enable
R/W
2
–
0
2
0
Reserved
Cap0 Fall
Enable
R/W
1
–
0
1
0
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CY7C638xx
CY7C639xx
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Cap0 Rise
Enable
R/W
0
–
0
0
0