CY7C63923-PVXC Cypress Semiconductor Corp, CY7C63923-PVXC Datasheet - Page 31
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CY7C63923-PVXC
Manufacturer Part Number
CY7C63923-PVXC
Description
IC USB PERIPHERAL CTRLR 48-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet
1.CY7C63823-PXC.pdf
(68 pages)
Specifications of CY7C63923-PVXC
Controller Type
USB Peripheral Controller
Interface
USB
Voltage - Supply
4 V ~ 5.5 V
Current - Supply
40mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C63923-PVXC
Manufacturer:
CY
Quantity:
14
Part Number:
CY7C63923-PVXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document 38-08035 Rev. *E
14.2.12 P0.2/INT0 – P0.4/INT2 Configuration
Table 14-8. P0.2/INT0–P0.4/INT2 Configuration (P02CR–P04CR) [0x07–0x09] [R/W]
14.2.13 P0.5/TIO0 – P0.6/TIO1 Configuration
Table 14-9. P0.5/TIO0 – P0.6/TIO1 Configuration (P05CR–P06CR) [0x0A–0x0B] [R/W]
14.2.14 P0.7 Configuration
Table 14-10. P0.7 Configuration (P07CR) [0x0C] [R/W]
These registers control the operation of pins P0.2–P0.4 respectively. These pins are shared between the P0.2–P0.4 GPIOs and
the INT0–INT2. These registers exist in all enCoRe II parts. The INT0–INT2 interrupts are different than all the other GPIO
interrupts. These pins are connected directly to the interrupt controller to provide three edge-sensitive interrupts with independent
interrupt vectors. These interrupts occur on a rising edge when Int act Low is clear and on a falling edge when Int act Low is set.
These pins are enabled as interrupt sources in the interrupt controller registers (Table 17-8 and Table 17-6).
To use these pins as interrupt inputs configure them as inputs by clearing the corresponding Output Enable. If the INT0–INT2
pins are configured as outputs with interrupts enabled, firmware can generate an interrupt by writing the appropriate value to the
P0.2, P0.3 and P0.4 data bits in the P0 Data Register
Regardless of whether the pins are used as Interrupt or GPIO pins the Int Enable, Int act Low, TTL Threshold, Open Drain, and
Pull-up Enable bits control the behavior of the pin
The P0.2/INT0–P0.4/INT2 pins are individually configured with the P02CR (0x07), P03CR (0x08), and P04CR (0x09) respec-
tively.
Note: Changing the state of the Int Act Low bit can cause an unintentional interrupt to be generated. When configuring these
interrupt sources, it is best to follow the following procedure:
These registers control the operation of pins P0.5 through P0.6, respectively. These registers exist in all enCoRe II parts.
P0.5 and P0.6 are shared with TIO0 and TIO1, respectively. To use these pins as Capture Timer inputs, configure them as inputs
by clearing the corresponding Output Enable. To use TIO0 and TIO1 as Timer outputs, set the TIOx Output and Output Enable
bits. If these pins are configured as outputs and the TIO Output bit is clear, firmware can control the TIO0 and TIO1 inputs by
writing the value to the P0.5 and P0.6 data bits in the P0 Data Register
Regardless of whether either pin is used as a TIO or GPIO pin the Int Enable, Int act Low, TTL Threshold, Open Drain, and Pull-
up Enable control the behavior of the pin.
TIO0(P0.5) when enabled outputs a positive pulse from the 1024-µs interval timer. This is the same signal that is used internally
to generate the 1024-µs timer interrupt. This signal is not gated by the interrupt enable state.
TIO1(P0.6) when enabled outputs a positive pulse from the programmable interval timer. This is the same signal that is used
internally to generate the programmable timer interval interrupt. This signal is not gated by the interrupt enable state
The P0.5/TIO0 and P0.6/TIO1 pins are individually configured with the P05CR (0x0A) and P06CR (0x0B), respectively
This register controls the operation of pin P0.7. The P0.7 pin only exists in the CY7C638xx and CY7C639xx
1. Disable interrupt source
2. Configure interrupt source
3. Clear any pending interrupts from the source
4. Enable interrupt source
Read/Write
Read/Write
Read/Write
Default
Default
Default
Field
Field
Field
Bit #
Bit #
Bit #
TIO Output
Reserved
7
–
0
7
–
0
7
–
0
Reserved
Int Enable
Int Enable
R/W
R/W
6
–
0
6
0
6
0
Int Act Low
Int Act Low
Int Act Low
R/W
R/W
R/W
5
0
5
0
5
0
TTL Thresh
TTL Thresh
TTL Thresh
R/W
R/W
R/W
4
0
4
0
4
0
Reserved
Reserved
Reserved
3
–
0
3
–
0
3
–
0
Open Drain
Open Drain
Open Drain
R/W
R/W
R/W
2
0
2
0
2
0
Pull-up Enable
Pull-up Enable
Pull-up Enable
R/W
R/W
R/W
1
0
1
0
1
0
CY7C63310
CY7C638xx
CY7C639xx
Page 31 of 68
Output Enable
Output Enable
Output Enable
R/W
R/W
R/W
0
0
0
0
0
0