CY7C63923-PVXC Cypress Semiconductor Corp, CY7C63923-PVXC Datasheet - Page 6

• Manufacturer Part Number: CY7C63923-PVXC
• Description: IC USB PERIPHERAL CTRLR 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63923-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Document 38-08035 Rev. *E
Table 5-1. Pin Assignments (continued)
Note:
SSOP
1,2,3,
1.
25
26
28
29
30
31
32
33
23
22
21
20
19
18
17
16
48
4
P1.0(D+) and P1.1(D-) pins should be in I/O mode when used as GPIO and in I
PDIP
21
22
24
25
26
27
28
29
19
18
17
16
15
14
13
12
40
SSOP
15
16
18
19
20
21
22
23
13
12
11
10
28
9
8
7
6
QSOP
14
15
17
18
21
22
23
24
24
9
8
7
6
5
4
3
2
1
SOIC
13
14
16
17
20
21
22
23
24
9
8
7
6
5
4
3
2
1
PDIP
20
21
23
24
16
15
14
13
12
11
10
24
3
4
5
6
9
7
SIOC
18
10
11
13
14
15
16
17
18
8
7
6
5
4
3
2
1
PDIP
15
18
13
16
12
11
10
18
1
2
3
4
5
9
8
7
6
SOIC
13
10
12
14
15
16
16
9
7
6
5
4
3
2
1
PDIP
13
14
16
10
16
11
1
2
3
4
9
8
7
6
5
Pad
1,2,
Die
3,4
25
26
28
29
30
31
32
33
23
22
21
20
19
18
17
16
SB
mode.
P1.0/D+
P1.1/D–
P1.2/VREG
P1.3/SSEL
P1.4/SCLK
P1.5/SMOSI
P1.6/SMISO
P1.7
P0.0/CLKIN
P0.1 /
CLKOUT
P0.2/INT0
P0.3/INT1
P0.4/INT2
P0.5/TIO0
P0.6/TIO1
P0.7
NC
Name
GPIO Port 1 bit 0 / USB D+
GPIO Port 1 bit 1 / USB D–
GPIO Port 1 bit 2—Configured individually.
3.3V if regulator is enabled. (The 3.3V
regulator is not available in the
CY7C63310 and CY7C63801.)
GPIO Port 1 bit 3—Configured individually.
Alternate function is SSEL signal of the
SPI bus TTL voltage thresholds
GPIO Port 1 bit 4—Configured individually.
Alternate function is SCLK signal of the
SPI bus TTL voltage thresholds
GPIO Port 1 bit 5—Configured individually.
Alternate function is SMOSI signal of the
SPI bus TTL voltage thresholds
GPIO Port 1 bit 6—Configured individually.
Alternate function is SMISO signal of the
SPI bus TTL voltage thresholds
GPIO Port 1 bit 7—Configured individually.
TTL voltage threshold.
GPIO Port 0 bit 0—Configured individually.
On CY7C639xx, optional Clock In when
external crystal oscillator is disabled or
crystal input when external crystal oscil-
lator is enabled.
On CY7C638xx and CY7C63310, oscil-
lator input when configured as Clock In
GPIO Port 0 bit 1—Configured individually
On CY7C639xx, optional clock out when
external crystal oscillator is disabled or
crystal output drive when external crystal
oscillator is enabled.
On CY7C638xx and CY7C63310, oscil-
lator output when configured as Clock out.
GPIO port 0 bit 2—Configured individually
Optional rising edge interrupt INT0
GPIO port 0 bit 3—Configured individually
Optional rising edge interrupt INT1
GPIO port 0 bit 4—Configured individually
Optional rising edge interrupt INT2
GPIO port 0 bit 5—Configured individually
Alternate function Timer capture inputs or
Timer output TIO0
GPIO port 0 bit 6—Configured individually
Alternate function Timer capture inputs or
Timer output TIO1
GPIO port 0 bit 7—Configured individually
Not in 16 pin PDIP or SOIC package
No connect
Description
CY7C63310
CY7C638xx
CY7C639xx
[1]
[1]
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