CY7C63923-PVXC Cypress Semiconductor Corp, CY7C63923-PVXC Datasheet - Page 58
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CY7C63923-PVXC
Manufacturer Part Number
CY7C63923-PVXC
Description
IC USB PERIPHERAL CTRLR 48-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet
1.CY7C63823-PXC.pdf
(68 pages)
Specifications of CY7C63923-PVXC
Controller Type
USB Peripheral Controller
Interface
USB
Voltage - Supply
4 V ~ 5.5 V
Current - Supply
40mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C63923-PVXC
Manufacturer:
CY
Quantity:
14
Part Number:
CY7C63923-PVXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document 38-08035 Rev. *E
27.0
Note:
T
SPI Timing
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Parameter
8.
Non-USB Mode Driver Characteristics
FPS2
SMCK
SSCK
SCKH
SCKL
MDO
MDO1
MSU
MHD
SSU
SHD
SDO
SDO1
SSS
SSH
In Master mode first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.
AC Characteristics
SDATA/SCK Transition Fall Time
SPI Master Clock Rate
SPI Slave Clock Rate
SPI Clock High Time
SPI Clock Low Time
Master Data Output Time
Master Data Output Time,
First bit with CPHA = 0
Master Input Data Set-up time
Master Input Data Hold time
Slave Input Data Set-up Time
Slave Input Data Hold Time
Slave Data Output Time
Slave Data Output Time,
First bit with CPHA = 0
Slave Select Set-up Time
Slave Select Hold Time
Description
V
V
V
CLOCK
oh
ol
crs
(continued)
D +
D −
[8]
10%
Figure 27-2. USB Data Signal Timing
T
R
Figure 27-1. Clock Timing
90%
After last SCK edge
F
High for CPOL = 0, Low for CPOL = 1
Low for CPOL = 0, High for CPOL = 1
SCK to data valid
Time before leading SCK edge
SCK to data valid
Time after SS LOW to data valid
Before first SCK edge
CPUCLK
T
CH
/6
T
CYC
Conditions
90%
T
CL
T
F
10%
Min.
125
125
–25
100
150
150
50
50
50
50
50
Typical
CY7C63310
CY7C638xx
CY7C639xx
Max.
300
100
100
2.2
Page 58 of 68
50
2
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns