CY7C63923-PVXC Cypress Semiconductor Corp, CY7C63923-PVXC Datasheet - Page 11
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CY7C63923-PVXC
Manufacturer Part Number
CY7C63923-PVXC
Description
IC USB PERIPHERAL CTRLR 48-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet
1.CY7C63823-PXC.pdf
(68 pages)
Specifications of CY7C63923-PVXC
Controller Type
USB Peripheral Controller
Interface
USB
Voltage - Supply
4 V ~ 5.5 V
Current - Supply
40mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C63923-PVXC
Manufacturer:
CY
Quantity:
14
Part Number:
CY7C63923-PVXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document 38-08035 Rev. *E
Examples
7.2.7
The result of an instruction using this addressing mode is
placed within either the RAM memory space or the register
space. Operand 1 is added to the X register to form the
address of the result. The source for the instruction is Operand
2, which is an immediate value. Arithmetic instructions require
two sources; the second source is the location specified by
Operand 1 added with the X register. Instructions using this
addressing mode are three bytes in length.
Table 7-13. Destination Indexed Immediate
Examples
7.2.8
The result of an instruction using this addressing mode is
placed within the RAM memory. Operand 1 is the address of
the result. Operand 2 is an address that points to a location in
the RAM memory that is the source for the instruction. This
addressing mode is only valid on the MOV instruction. The
instruction using this addressing mode is three bytes in length.
Table 7-14. Destination Direct
ADD
MOV
Instruction
ADD
MOV
Instruction
Opcode
Opcode
[7],
REG[8],
[X+7],
REG[X+8],
Destination Indexed Immediate
Destination Direct
Destination Address
Destination Index
5
6
Operand 1
Operand 1
5
6
;In this case, value in the mem-
;ory location at address 7 is
;added to the immediate value of
;5, and the result is placed in
;the memory location at address 7.
;In this case, the immediate
;value of 6 is moved into the
;register space location at
;address 8.
;In this case, the value in
;the memory location at
;address X+7 is added with
;the immediate value of 5,
;and the result is placed
;in the memory location at
;address X+7.
;In this case, the immedi-
;ate value of 6 is moved
;into the location in the
;register space at
;address X+8.
Immediate Value
Source Address
Operand 2
Operand 2
Example
7.2.9
The result of an instruction using this addressing mode is
placed in the Accumulator. Operand 1 is an address pointing
to a location within the memory space, which contains an
address (the indirect address) for the source of the instruction.
The indirect address is incremented as part of the instruction
execution. This addressing mode is only valid on the MVI
instruction. The instruction using this addressing mode is two
bytes in length. Refer to the PSoC Designer: Assembly
Language User Guide for further details on MVI instruction.
Table 7-15. Source Indirect Post Increment
Example
7.2.10
The result of an instruction using this addressing mode is
placed within the memory space. Operand 1 is an address
pointing to a location within the memory space, which contains
an address (the indirect address) for the destination of the
instruction. The indirect address is incremented as part of the
instruction execution. The source for the instruction is the
Accumulator. This addressing mode is only valid on the MVI
instruction. The instruction using this addressing mode is two
bytes in length.
Table 7-16. Destination Indirect Post Increment
Example
MOV
Instruction
MVI
Instruction
MVI
Opcode
Opcode
[7], [8] ;In this case, the value in the
A,
Source Indirect Post Increment
Destination Indirect Post Increment
[8],
[8]
A
;memory location at address 8 is
;moved to the memory location at
;address 7.
;In this case, the value in the
;memory location at address 8 is
;an indirect address. The memory
;location pointed to by the indi-
;rect address is moved into the
;Accumulator. The indirect
;address is then incremented.
Destination Address Address
Source Address Address
;In this case, the value in
;the memory location at
;address 8 is an indirect
;address. The Accumulator is
;moved into the memory loca-
;tion pointed to by the indi-
;rect address. The indirect
;address is then incremented.
Operand 1
Operand 1
CY7C63310
CY7C638xx
CY7C639xx
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