PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 100

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
7.1
The operation of the interface is controlled by the
MEMCON register (Register 7-1). This register is
available in all program memory operating modes
except Microcontroller mode. In this mode, the register
is disabled and cannot be written to.
The EBDIS bit (MEMCON<7>) controls the operation
of the bus and related port functions. Clearing EBDIS
enables the interface and disables the I/O functions of
the ports, as well as any other functions multiplexed to
those pins. Setting the bit enables the I/O ports and
other functions but allows the interface to override
everything else on the pins when an external memory
operation is required. By default, the external bus is
always enabled and disables all other I/O.
REGISTER 7-1:
DS39646B-page 98
External Memory Bus Control
bit 7
bit 6
bit 5-4
bit 3-2
bit 1-0
MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER
EBDIS: External Bus Disable bit
1 = External bus enabled when microcontroller accesses external memory;
0 = External bus always enabled, I/O ports are disabled
Unimplemented: Read as ‘0’
WAIT1:WAIT0: Table Reads and Writes Bus Cycle Wait Count bits
11 = Table reads and writes will wait 0 T
10 = Table reads and writes will wait 1 T
01 = Table reads and writes will wait 2 T
00 = Table reads and writes will wait 3 T
Unimplemented: Read as ‘0’
WM1:WM0: TBLWT Operation with 16-bit Data Bus Width Select bits
1x = Word Write mode: TABLAT0 and TABLAT1 word output, WRH active when
01 = Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB)
00 = Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate
bit7
Legend:
R = Readable bit
-n = Value at POR
EBDIS
R/W-0
otherwise, all external bus drivers are mapped as I/O ports
TABLAT1 written
will activate
U-0
—
WAIT1
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
WAIT0
R/W-0
CY
CY
CY
CY
The operation of the EBDIS bit is also influenced by the
program memory mode being used. This is discussed
in more detail in Section 7.4 “Program Memory
Modes and the External Memory Bus”.
The WAIT bits allow for the addition of wait states to
external memory operations. The use of these bits is
discussed in Section 7.3 “Wait States”.
The WM bits select the particular operating mode used
when the bus is operating in 16-bit Data Width mode.
These are discussed in more detail in Section 7.5
“16-bit Data Width Modes”. These bits have no effect
when an 8-bit Data Width mode is selected.
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
U-0
—
 2004 Microchip Technology Inc.
x = Bit is unknown
R/W-0
WM1
R/W-0
WM0
bit0