PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 152

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
TABLE 11-11: PORTF FUNCTIONS
TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
DS39646B-page 150
RF0/AN5
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CV
RF6/AN11
RF7/SS1
Legend:
TRISF
PORTF
LATF
ADCON1
CMCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
Name
Pin Name
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
REF
TRISF7
C2OUT
LATF7
Bit 7
RF7
—
Function
C2OUT
C1OUT
CV
AN10
AN11
RF0
AN5
RF1
AN6
RF2
AN7
RF3
AN8
RF4
AN9
RF5
RF6
RF7
SS1
REF
TRISF6
C1OUT
LATF6
Bit 6
RF6
Setting
—
TRIS
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
1
1
x
0
1
1
0
1
1
TRISF5
VCFG1
C2INV
LATF5
I/O
O
O
O
O
O
O
O
O
O
O
O
Bit 5
RF5
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
DIG
DIG
TTL
I/O
ST
ST
ST
ST
ST
ST
ST
ST
TRISF4
VCFG0
Preliminary
LATF4
C1INV
Bit 4
RF4
LATF<0> data output; not affected by analog input.
PORTF<0> data input; disabled when analog input enabled.
A/D input channel 5. Default configuration on POR.
LATF<1> data output; not affected by analog input.
PORTF<1> data input; disabled when analog input enabled.
A/D input channel 6. Default configuration on POR.
Comparator 2 output; takes priority over port data.
LATF<2> data output; not affected by analog input.
PORTF<2> data input; disabled when analog input enabled.
A/D input channel 7. Default configuration on POR.
Comparator 1 output; takes priority over port data.
LATF<3> data output; not affected by analog input.
PORTF<3> data input; disabled when analog input enabled.
A/D input channel 8 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
LATF<4> data output; not affected by analog input.
PORTF<4> data input; disabled when analog input enabled.
A/D input channel 9 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
LATF<5> data output; not affected by analog input. Disabled when
CV
PORTF<5> data input; disabled when analog input enabled. Disabled
when CV
A/D input channel 10 and Comparator C1+ input. Default input
configuration on POR; not affected by analog output.
Comparator voltage reference output. Enabling this feature disables
digital I/O.
LATF<6> data output; not affected by analog input.
PORTF<6> data input; disabled when analog input enabled.
A/D input channel 11 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
LATF<7> data output.
PORTF<7> data input.
Slave select input for SSP (MSSP1 module).
REF
output enabled.
TRISF3
PCFG3
LATF3
REF
Bit 3
RF3
CIS
output enabled.
TRISF2
PCFG2
LATF2
Bit 2
CM2
RF2
Description
TRISF1
PCFG1
LATF1
Bit 1
CM1
RF1
 2004 Microchip Technology Inc.
TRISF0
PCFG0
LATF0
Bit 0
CM0
RF0
on page
Values
Reset
60
60
60
59
59