PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 154

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
TABLE 11-13: PORTG FUNCTIONS
DS39646B-page 152
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG4/CCP5/P1D
RG5/MCLR/V
Legend:
Note 1:
Pin Name
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
RG5 does not have a corresponding TRISG bit.
PP
Function
ECCP3
MCLR
CCP4
CCP5
RG0
RG1
RG2
RG3
RG4
RG5
P3A
TX2
CK2
RX2
DT2
P3D
P1D
V
PP
Setting
TRIS
—
—
—
0
1
0
1
0
0
1
0
0
1
0
1
1
1
1
0
1
0
1
0
0
1
0
1
0
(1)
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
Preliminary
LATG<0> data output.
PORTG<0> data input.
ECCP3 compare and ECCP3 PWM output. Takes priority over
port data.
ECCP3 capture input.
ECCP3 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATG<1> data output.
PORTG<1> data input.
Asynchronous serial transmit data output (EUSART2 module). Takes
priority over port data.
Synchronous serial clock output (EUSART2 module). Takes priority
over port data.
Synchronous serial clock input (EUSART2 module).
LATG<2> data output.
PORTG<2> data input.
Asynchronous serial receive data input (EUSART2 module).
Synchronous serial data output (EUSART2 module). Takes priority
over port data. User must configure as an input.
Synchronous serial data input (EUSART2 module). User must
configure as an input.
LATG<3> data output.
PORTG<3> data input.
CCP4 compare and PWM output; takes priority over port data and
P3D function.
CCP4 capture input.
ECCP3 Enhanced PWM output, channel D. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATG<4> data output.
PORTG<4> data input.
CCP5 compare and PWM output. Takes priority over port data and
P1D function.
CCP5 capture input.
ECCP1 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
PORTG<5> data input; enabled when MCLRE configuration bit
is clear.
External Master Clear input; enabled when MCLRE configuration
bit is set.
High-voltage detection; used for ICSP™ mode entry detection.
Always available regardless of pin mode.
Description
 2004 Microchip Technology Inc.