PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 108

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
7.6
In 8-bit Data Width mode, the external memory bus
operates only in Multiplexed mode; that is, data shares
the 8 least significant bits of the address bus.
Figure 7-7 shows an example of 8-bit Multiplexed
mode for PIC18F8527/8622/8627/8722 devices. This
mode is used for a single 8-bit memory connected for
16-bit operation. The instructions will be fetched as two
8-bit bytes on a shared data/address bus. The two
bytes are sequentially fetched within one instruction
cycle (T
external memory devices according to timing calcula-
tions based on 1/2 T
For proper memory speed selection, glue logic
propagation delay times must be considered along with
setup and hold times.
FIGURE 7-7:
DS39646B-page 106
CY
8-bit Data Width Modes
). Therefore, the designer must choose
Note 1:
PIC18F8X27/8X22
2:
AD<15:8>
CY
A<19:16>
Upper-order address bits are used only for 20-bit address width. The upper AD byte is used
for all address widths except 8-bit.
This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
8-BIT MULTIPLEXED MODE EXAMPLE
AD<7:0>
(2 times the instruction rate).
WRL
ALE
BA0
OE
CE
(1)
(1)
Preliminary
373
The Address Latch Enable (ALE) pin indicates that the
address bits A<15:0> are available on the External
Memory Interface bus. The Output Enable signal (OE)
will enable one byte of program memory for a portion of
the instruction cycle, then BA0 will change and the sec-
ond byte will be enabled to form the 16-bit instruction
word. The least significant bit of the address, BA0,
must be connected to the memory devices in this
mode. The Chip Enable signal (CE) is active at any
time that the microcontroller accesses external
memory, whether reading or writing; it is inactive
(asserted high) whenever the device is in Sleep mode.
This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
The appropriate level of BA0 control line is strobed on
the LSb of the TBLPTR.
D<7:0>
A<19:0>
D<15:8>
Address Bus
Data Bus
Control Lines
 2004 Microchip Technology Inc.
A0
A<x:1>
D<7:0>
CE
OE
WR
(2)