PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 434
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PIC18F8722-I/PT
Manufacturer Part Number
PIC18F8722-I/PT
Description
80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F8722-IPT.pdf
(448 pages)
Specifications of PIC18F8722-I/PT
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
70
Interface
SPI/I2C/USART
Memory Type
Flash
Number Of Bits
8
Package Type
80-pin TQFP
Programmable Memory
128K Bytes
Ram Size
3.9K Bytes
Speed
40 MHz
Timers
2-8 bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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PIC18F8722 FAMILY
Brown-out Reset (BOR) ..................................................... 52
BSF .................................................................................. 333
BTFSC ............................................................................. 334
BTFSS .............................................................................. 334
BTG .................................................................................. 335
BZ ..................................................................................... 336
C
C Compilers
CALL ................................................................................ 336
CALLW ............................................................................. 365
Capture (CCP Module) ..................................................... 181
Capture (ECCP Module) .................................................. 192
Capture/Compare/PWM (CCP) ........................................ 179
Clock Sources .................................................................... 37
CLRF ................................................................................ 337
CLRWDT .......................................................................... 337
Code Examples
DS39646B-page 432
Detecting .................................................................... 52
Disabling in Sleep Mode ............................................ 52
Software Enabled ....................................................... 52
MPLAB C17 ............................................................. 372
MPLAB C18 ............................................................. 372
MPLAB C30 ............................................................. 372
Associated Registers ............................................... 183
CCPRxH:CCPRxL Registers ................................... 181
CCPx Pin Configuration ........................................... 181
Prescaler .................................................................. 181
Software Interrupt .................................................... 181
Timer1/Timer3 Mode Selection ................................ 181
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................ 180
CCPRxH Register .................................................... 180
CCPRxL Register ..................................................... 180
Compare Mode. See Compare.
Interconnect Configurations ..................................... 180
Module Configuration ............................................... 180
Selecting the 31 kHz Source ...................................... 38
Selection Using OSCCON Register ........................... 38
16 x 16 Signed Multiply Routine .............................. 118
16 x 16 Unsigned Multiply Routine .......................... 118
8 x 8 Signed Multiply Routine .................................. 117
8 x 8 Unsigned Multiply Routine .............................. 117
Changing Between Capture Prescalers ................... 181
Computed GOTO Using an Offset Value ................... 68
Data EEPROM Read ............................................... 113
Data EEPROM Refresh Routine .............................. 114
Data EEPROM Write ............................................... 113
Erasing a Flash Program Memory Row ..................... 92
Fast Register Stack .................................................... 68
How to Clear RAM (Bank 1)
Implementing a Real-Time Clock
Initializing PORTA .................................................... 135
Initializing PORTB .................................................... 137
Initializing PORTC .................................................... 140
Initializing PORTD .................................................... 143
Initializing PORTE .................................................... 146
Initializing PORTF .................................................... 149
Initializing PORTG ................................................... 151
Initializing PORTH .................................................... 154
Initializing PORTJ .................................................... 156
Loading the SSP1BUF
Using Indirect Addressing .................................. 81
Using a Timer1 Interrupt Service ..................... 169
(SSP1SR) Register .......................................... 208
Preliminary
Code Protection ............................................................... 297
COMF .............................................................................. 338
Comparator ...................................................................... 281
Comparator Specifications ............................................... 396
Comparator Voltage Reference ....................................... 287
Comparator Voltage
Compare (CCP Module) .................................................. 182
Compare (CCP Modules)
Compare (ECCP Module) ................................................ 192
Compare (ECCP2 Module)
Computed GOTO ............................................................... 68
Configuration Bits ............................................................ 297
Configuration Register Protection .................................... 320
Context Saving During Interrupts ..................................... 134
Conversion Considerations .............................................. 428
CPFSEQ .......................................................................... 338
CPFSGT .......................................................................... 339
CPFSLT ........................................................................... 339
Crystal Oscillator/Ceramic Resonator ................................ 31
D
Data Addressing Modes .................................................... 81
Data EEPROM
Reading a Flash Program Memory Word .................. 91
Saving STATUS, WREG and
Writing to Flash Program Memory ....................... 94–95
Analog Input Connection Considerations ................ 285
Associated Registers ............................................... 285
Configuration ........................................................... 282
Effects of a Reset .................................................... 284
Interrupts ................................................................. 284
Operation ................................................................. 283
Operation During Sleep ........................................... 284
Outputs .................................................................... 283
Reference ................................................................ 283
Response Time ........................................................ 283
Accuracy and Error .................................................. 288
Associated Registers ............................................... 289
Configuring .............................................................. 287
Connection Considerations ...................................... 288
Effects of a Reset .................................................... 288
Operation During Sleep ........................................... 288
Reference Specifications ......................................... 396
Associated Registers ............................................... 183
CCPRx Registers ..................................................... 182
Pin Configuration ..................................................... 182
Software Interrupt .................................................... 182
Special Event Trigger .............................................. 182
Timer1/Timer3 Mode Selection ................................ 182
Special Event Trigger .............................................. 175
Special Event Trigger .............................................. 192
Special Event Trigger .............................................. 280
Comparing Addressing Modes with
Direct ......................................................................... 81
Indexed Literal Offset ................................................ 83
Indirect ....................................................................... 81
Inherent and Literal .................................................... 81
Code Protection ....................................................... 320
BSR Registers in RAM .................................... 134
External Signal ................................................ 283
Internal Signal .................................................. 283
the Extended Instruction Set Enabled ............... 84
Instructions Affected .......................................... 83
2004 Microchip Technology Inc.
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