DP83849CVS/NOPB National Semiconductor, DP83849CVS/NOPB Datasheet - Page 74

• Manufacturer Part Number: DP83849CVS/NOPB
• Description: IC TXRX ETHERNET PHY DUAL 80TQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83849CVS/NOPB

• Number Of Drivers/receivers: 2/2
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 80
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• For Use With: DP83849CVS-EVK - BOARD EVALUATION DP83849CVS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83849CVS; *DP83849CVS/NOPB; DP83849CVS

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7.3.9 Link Quality Monitor Register (LQMR), Page 2, address 1Dh
This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides a mechanism
for programming a set of thresholds for DSP parameters. If the thresholds are violated, an interrupt will be asserted if
enabled in the MISR. Monitor control and status are available in this register, while the LQDR register controls read/write
access to threshold values and current parameter values. Reading of LQMR register clears warning bits and re-arms the
interrupt generation. In addition, this register provides a mechanims for allowing automatic reset of the 100Mb link based
on the Link Quality Monitor status
14:10
Bit
15
9
8
7
6
5
4
3
2
1
0
DBLW_LO_WARN
DAGC_LO_WARN
FREQ_LO_WARN
DBLW_HI_WARN
DAGC_HI_WARN
FREQ_HI_WARN
FC_LO_WARN
C1_LO_WARN
LQM_ENABLE
FC_HI_WARN
C1_HI_WARN
RESERVED
Bit Name
Table 51. Link Quality Monitor Register (LQMR), address 1Dh
.
0, RO/COR
0, RO/COR
0, RO/COR
0, RO/COR
0, RO/COR
0, RO/COR
0, RO/COR
0, RO/COR
0, RO/COR
0, RO/COR
Default
0, RW
0, RO
Link Quality Monitor Enable:
Enables the Link Quality Monitor. The enable is qualified by having
a valid 100Mb link. In addition, the individual thresholds can be dis-
abled by setting to the max or min values.
RESERVED: Writes ignored, read as 0.
Frequency Control High Warning:
This bit indicates the Frequency Control High Threshold was ex-
ceeded. This register bit will be cleared on read.
Frequency Control Low Warning:
This bit indicates the Frequency Control Low Threshold was ex-
ceeded. This register bit will be cleared on read.
Frequency Offset High Warning:
This bit indicates the Frequency Offset High Threshold was ex-
ceeded. This register bit will be cleared on read.
Frequency Offset Low Warning:
This bit indicates the Frequency Offset Low Threshold was exceed-
ed. This register bit will be cleared on read.
DBLW High Warning:
This bit indicates the DBLW High Threshold was exceeded. This
register bit will be cleared on read.
DBLW Low Warning:
This bit indicates the DBLW Low Threshold was exceeded. This
register bit will be cleared on read.
DAGC High Warning:
This bit indicates the DAGC High Threshold was exceeded. This
register bit will be cleared on read.
DAGC Low Warning:
This bit indicates the DAGC Low Threshold was exceeded. This
register bit will be cleared on read.
C1 High Warning:
This bit indicates the DEQ C1 High Threshold was exceeded. This
register bit will be cleared on read.
C1 Low Warning:
This bit indicates the DEQ C1 Low Threshold was exceeded. This
register bit will be cleared on read.
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Description