PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 146

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24FJ256GB210 FAMILY
8.5.2
In
PIC24FJ256GB210 family of devices, the primary
oscillator with the PLL block can be used as a valid
clock source for USB operation. The FRC oscillator
(implemented with ±1.0% accuracy) can be combined
with a PLL block, providing another option for a valid
USB clock source. There is no provision to provide a
separate external 48 MHz clock to the USB module.
TABLE 8-3:
DS39975A-page 146
Note:
Input Oscillator Frequency
the
For USB devices, the use of a primary oscillator or external clock source, with a frequency above 32 MHz,
does not imply that the device’s system clock can be run at the same speed when the USB module is not
used. The maximum system clock for all PIC24F devices is 32 MHz.
USB CLOCK GENERATION
USB-On-The-Go
48 MHz
32 MHz
24 MHz
20 MHz
16 MHz
12 MHz
8 MHz
4 MHz
VALID OSCILLATOR CONFIGURATIONS FOR USB OPERATIONS
module
ECPLL, HSPLL, XTPLL, FRCPLL
ECPLL, HSPLL, XTPLL, FRCPLL
in
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
Clock Mode
the
ECPLL
The USB module sources its clock signal from a
96 MHz PLL. Due to the requirement that a 4 MHz input
must be provided to generate the 96 MHz signal, the
oscillator operation is limited to a range of possible val-
ues. Table 8-3 shows the valid oscillator configurations
(i.e., ECPLL, HSPLL, XTPLL and FRCPLL) for USB
operation. This sets the correct PLLDIV configuration
for the specified oscillator frequency and the output
frequency of the USB clock branch is always 48 MHz.
 2010 Microchip Technology Inc.
(PLLDIV<2:0>)
PLL Division
12 (111)
8 (110)
6 (101)
5 (100)
4 (011)
3 (010)
2 (001)
1 (000)