PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 196

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24FJ256GB210 FAMILY
FIGURE 14-1:
14.2
In Compare mode (Figure 14-1), the output compare
module can be configured for single-shot or continuous
pulse generation. It can also repeatedly toggle an
output pin on each timer event.
To set up the module for compare operations:
1.
2.
DS39975A-page 196
Trigger and
Sync Sources
OC Clock
Sources
Configure the OCx output for one of the
available Peripheral Pin Select pins.
Calculate the required values for the OCxR and
(for Double Compare modes) OCxRS Duty Cycle
registers:
a)
b)
c)
Note 1: The OCx outputs must be assigned to an available RPn pin before use. See Section 10.4 “Peripheral Pin
Compare Operations
Determine the instruction clock cycle time.
Take into account the frequency of the
external clock to the timer source (if one is
used) and the timer prescaler settings.
Calculate time to the rising edge of the
output pulse relative to the timer start value
(0000h).
Calculate the time to the falling edge of the
pulse based on the desired pulse width and
the time to the rising edge of the pulse.
2: The OCFA/OCFB Fault inputs must be assigned to an available RPn/RPIn pin before use. See Section 10.4
Select (PPS)” for more information.
“Peripheral Pin Select (PPS)” for more information.
TRIGMODE
SYNCSELx
TRIGSTAT
OCTSELx
OCTRIG
Trigger and
Sync Logic
OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE)
Select
Clock
Match Event
Reset
Increment
Reset
OCxR and
Comparator
Comparator
DCB<1:0>
OCxCON1
OCxCON2
OCxTMR
OCxRS
3.
4.
5.
6.
7.
8.
Match Event
Match Event
Write the rising edge value to OCxR and the
falling edge value to OCxRS.
Set the Timer Period register, PRy, to a value
equal to or greater than the value in OCxRS.
Set the OCM<2:0> bits for the appropriate
compare operation (= 0xx).
For Trigger mode operations, set OCTRIG to
enable Trigger mode. Set or clear TRIGMODE to
configure trigger operation and TRIGSTAT to
select a hardware or software trigger. For
Synchronous mode, clear OCTRIG.
Set the SYNCSEL<4:0> bits to configure the
trigger or synchronization source. If free-running
timer operation is required, set the SYNCSEL
bits to ‘00000’ (no sync/trigger source).
Select
OCTSEL<2:0> bits. If necessary, set the TON
bits for the selected timer, which enables the
compare time base to count. Synchronous
mode operation starts as soon as the time base
is enabled; Trigger mode operation starts after a
trigger source event occurs.
the
OC Output and
Fault Logic
OCx Interrupt
time
OCMx
OCINV
OCTRIS
FLTOUT
FLTTRIEN
FLTMD
ENFLT<2:0>
OCFLT<2:0>
DCB<1:0>
 2010 Microchip Technology Inc.
base
source
OCFA/OCFB
OCx Pin
with
(1)
the
(2)