PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 304

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24FJ256GB210 FAMILY
REGISTER 22-2:
DS39975A-page 304
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6-2
bit 1
bit 0
R-0, HSC
VCFG2
R/W-0
BUFS
VCFG<2:0>: Voltage Reference Configuration bits
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
CSCNA: Scan Input Selections for the CH0+ S/H Input for MUX A Input Multiplexer Setting bit
1 = Scan inputs
0 = Do not scan inputs
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = A/D is currently filling buffer, 10-1F, user should access data in 00-0F
0 = A/D is currently filling buffer, 00-0F, user should access data in 10-1F
SMPI<4:0>: Sample/Convert Sequences Per Interrupt Selection bits
11111 = Interrupts at the completion of conversion for each 32
11110 = Interrupts at the completion of conversion for each 31
.
.
.
00001 = Interrupts at the completion of conversion for each 2
00000 = Interrupts at the completion of conversion for each sample/convert sequence
BUFM: Buffer Mode Select bit
1 = Buffer is configured as two 16-word buffers (ADC1BUFn<31:16> and ADC1BUFn<15:0>)
0 = Buffer is configured as one 32-word buffer (ADC1BUFn<31:0>)
ALTS: Alternate Input Sample Mode Select bit
1 = Uses MUX A input multiplexer settings for the first sample, then alternates between MUX B and
0 = Always uses the MUX A input multiplexer settings
VCFG1
SMPI4
R/W-0
R/W-0
MUX A input multiplexer settings for all subsequent samples
VCFG<2:0>
AD1CON2: A/D CONTROL REGISTER 2
000
001
010
011
1xx
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
VCFG0
SMPI3
R/W-0
R/W-0
External V
External V
SMPI2
R/W-0
r-0
r
AV
AV
AV
V
R
DD
DD
DD
+
REF
REF
+ pin
+ pin
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SMPI1
R/W-0
U-0
—
External V
External V
CSCNA
SMPI0
R/W-0
R/W-0
nd
nd
st
sample/convert sequence
AV
AV
AV
sample/convert sequence
sample/convert sequence
V
R
SS
SS
SS
-
REF
REF
 2010 Microchip Technology Inc.
- pin
- pin
x = Bit is unknown
R/W-0
BUFM
U-0
—
R/W-0
ALTS
U-0
—
bit 8
bit 0