PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 69

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.2.5.1
In order to read the data from the EDS space, first, an
Address Pointer is set up by loading the required EDS
page number into the DSRPAG register and assigning
the offset address to one of the W registers. Once the
above assignment is done, the EDS window is enabled
FIGURE 4-5:
When the Most Significant bit (MSb) of EA is ‘1’ and
DSRPAG<9> = 0, the lower 9 bits of DSRPAG are con-
catenated to the lower 15 bits of EA to form a 24-bit
EDS space address for read operations.
Example 4-1 shows how to read a byte, word and
double-word from EDS.
EXAMPLE 4-1:
 2010 Microchip Technology Inc.
; Set the EDS page from where the data to be read
;Read a byte from the selected location
;Read a word from the selected location
;Read Double - word from the selected location
mov
mov
mov
bset
mov.b
mov.b
mov
mov.d
Data Read from EDS Space
#0x0002 , w0
w0 , DSRPAG
#0x0800 ,
w1 , #15
[w1++] , w2
[w1++] , w3
[w1] , w2
[w1] , w2
9
EDS ADDRESS GENERATION FOR READ OPERATIONS
0 = Extended SRAM and EPMP
EDS READ CODE IN ASSEMBLY
8
DSRPAG Reg
9 Bits
w1
Select
;page 2 is selected for read
;select the location (0x800) to be read
;set the MSB of the base address, enable EDS mode
;read Low byte
;read High byte
;
;two word read, stored in w2 and w3
0
1
PIC24FJ256GB210 FAMILY
24-Bit EA
Wn
by setting bit 15 of the working register, assigned with
the offset address; then, the contents of the pointed
EDS location can be read.
Figure 4-5 illustrates how the EDS space address is
generated for read operations.
15 Bits
Note:
All read operations from EDS space have
an overhead of one instruction cycle.
Therefore, a minimum of two instruction
cycles is required to complete an EDS
read. EDS reads under the REPEAT
instruction; the first two accesses take
three
accesses take one cycle.
Wn<0> is Byte Select
cycles
and
the
DS39975A-page 69
subsequent