PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 200

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24FJ256GB210 FAMILY
REGISTER 14-1:
DS39975A-page 200
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
Note 1:
ENFLT0
R/W-0
U-0
—
2:
3:
4:
(2)
The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4
“Peripheral Pin Select (PPS)”.
The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110.
The Comparator 1 output controls the OC1-OC3 channels; Comparator 2 output controls the OC4-OC6
channels. Comparator 3 output controls the OC7-OC9 channels.
The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information,
see Section 10.4 “Peripheral Pin Select (PPS)”.
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare x in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
OCTSEL<2:0>: Output Compare x Timer Select bits
111 = Peripheral clock (F
110 = Reserved
101 = Reserved
100 = Timer1 clock (only the synchronous clock is supported)
011 = Timer5 clock
010 = Timer4 clock
001 = Timer3 clock
000 = Timer2 clock
ENFLT2: Fault Input 2 Enable bit
1 = Fault 2 (Comparator 1/2/3 out) is enabled
0 = Fault 2 is disabled
ENFLT1: Fault Input 1 Enable bit
1 = Fault 1 (OCFB pin) is enabled
0 = Fault 1 is disabled
ENFLT0: Fault Input 0 Enable bit
1 = Fault 0 (OCFA pin) is enabled
0 = Fault 0 is disabled
OCFLT2: PWM Fault 2 (Comparator 1/2/3) Condition Status bit
1 = PWM Fault 2 has occurred
0 = No PWM Fault 2 has occurred
OCFLT1: PWM Fault 1 (OCFB pin) Condition Status bit
1 = PWM Fault 1 has occurred
0 = No PWM Fault 1 has occurred
OCFLT0: PWM Fault 0 (OCFA pin) Condition Status bit
1 = PWM Fault 0 has occurred
0 = No PWM Fault 0 has occurred
R/W-0, HSC R/W-0, HSC R/W-0, HSC
OCFLT2
U-0
—
OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
(2)
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
OCFLT1
OCSIDL
R/W-0
(2)
CY
)
OCFLT0
OCTSEL2
R/W-0
(2)
(2)
(2)
(4)
(4)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRIGMODE
OCTSEL1
(3)
R/W-0
R/W-0
(2,4)
(2,4)
OCTSEL0
OCM2
R/W-0
R/W-0
(2,3)
(1)
 2010 Microchip Technology Inc.
x = Bit is unknown
ENFLT2
OCM1
R/W-0
R/W-0
(1)
(2)
ENFLT1
OCM0
R/W-0
R/W-0
(1)
bit 8
bit 0
(2)