PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 35

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.7
If an ICSP compliant emulator is selected as a debug-
ger, it automatically initializes all of the A/D input pins
(ANx) as “digital” pins. Depending on the particular
device, this is done by clearing all bit in the ANSx reg-
isters.
All PIC24FJ devices will have several ANSx registers
(one for each port). Refer to (Section 10.0 “I/O Ports”)
for more specific information.
The bits in these registers that correspond to the A/D
pins that initialized the emulator must not be changed
by
communication errors will result between the debugger
and the device.
 2010 Microchip Technology Inc.
the
Configuration of Analog and
Digital Pins During ICSP
Operations
user
application
firmware;
otherwise,
PIC24FJ256GB210 FAMILY
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must modify the appropriate bits during
initialization of the ADC module, as follows:
• Set the bits corresponding to the pin(s) to be con-
When a Microchip debugger/emulator is used as a
programmer, the user application firmware must
correctly configure the ANSx registers. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all A/D pins being recognized as
analog input pins, resulting in the port value being read
as a logic ‘0’, which may affect user application
functionality.
2.8
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to V
output to logic low.
figured as analog. Do not change any other bits,
particularly those corresponding to the
PGECx/PGEDx pair, at any time.
Unused I/Os
SS
on unused pins and drive the
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