PIC16F631-I/P Microchip Technology Inc., PIC16F631-I/P Datasheet
PIC16F631-I/P
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PIC16F631-I/P Summary of contents
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... PIC16F631/677/685/687/689/690 © 2007 Microchip Technology Inc. Data Sheet 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology DS41262D ...
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... MCUs and dsPIC ® EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified logo, microID, MPLAB, PIC DSCs ® code hopping devices, Serial EE OQ © 2007 Microchip Technology Inc. ® ...
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... PIC16F631/677/685/687/689/690 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with High-Performance RISC CPU: • Only 35 instructions to learn: - All single-cycle instructions except branches • Operating speed – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt capability • 8-level deep hardware stack • Direct, Indirect and Relative Addressing modes Special Microcontroller Features: • ...
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... PIC16F689 4096 256 256 PIC16F690 4096 256 256 PIC16F631 Pin Diagram 20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/V RC4/C2OUT RC3/C12IN3- TABLE 1: PIC16F631 PIN SUMMARY I/O Pin Analog Comparators RA0 19 AN0/ULPWU RA1 18 AN1 RA2 17 — RA3 4 — RA4 3 — ...
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... PIC16F631/677/685/687/689/690 PIC16F677 Pin Diagram 20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC4/C2OUT RC3/AN7C12IN3- RC6/AN8/SS RC7/AN9/SDO TABLE 2: PIC16F677 PIN SUMMARY I/O Pin Analog Comparators RA0 19 AN0/ULPWU C1IN+ RA1 18 AN1/V C12IN0- REF RA2 17 AN2 C1OUT RA3 4 — RA4 3 AN3 RA5 2 — RB4 13 AN10 ...
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... PIC16F631/677/685/687/689/690 PIC16F685 Pin Diagram 20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC5/CCP1/P1A RC4/C2OUT/P1B RC3/AN7/C12IN3-/P1C TABLE 3: PIC16F685 PIN SUMMARY I/O Pin Analog Comparators RA0 19 AN0/ULPWU C1IN+ RA1 18 AN1/V C12IN0- REF RA2 17 AN2 C1OUT RA3 4 — RA4 3 AN3 RA5 2 — RB4 13 AN10 ...
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... PIC16F631/677/685/687/689/690 PIC16F687/689 Pin Diagram 20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC4/C2OUT RC3/AN7/C12IN3- RC6/AN8/SS RC7/AN9/SDO RB7/TX/CK TABLE 4: PIC16F687/689 PIN SUMMARY I/O Pin Analog Comparators RA0 19 AN0/ULPWU C1IN+ RA1 18 AN1/V C12IN0- REF RA2 17 AN2 C1OUT RA3 4 — — RA4 3 AN3 — RA5 2 — ...
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... PIC16F631/677/685/687/689/690 PIC16F690 Pin Diagram (PDIP, SOIC, SSOP) 20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC5/CCP1/P1A RC4/C2OUT/P1B RC3/AN7/C12IN3-/P1C RC6/AN8/SS RC7/AN9/SDO RB7/TX/CK TABLE 5: PIC16F690 PIN SUMMARY I/O Pin Analog Comparators Timers RA0 19 AN0/ULPWU C1IN+ RA1 18 AN1/V C12IN0- REF RA2 17 AN2 C1OUT RA3 4 — ...
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... RC6/AN8/SS Note 1: CCP1/P1A, P1B, P1C and P1D are available on PIC16F685/PIC16F690 only. 2: SS, SDO, SDI/SDA and SCL/SCK are available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 3: RX/DT and TX/CK are available on PIC16F687/PIC16F689/PIC16F690 only. © 2007 Microchip Technology Inc RA1/AN1/C12IN0-/ RA2/AN2/T0CKI/INT/C1OUT PIC16F631/677 RC0/AN4/C2IN+ 685/687/689/690 4 12 RC1/AN5/C12IN1 RC2/AN6/C12IN2-/P1D ...
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... PIC16F631/677/685/687/689/690 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Memory Organization ................................................................................................................................................................. 25 3.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 47 4.0 I/O Ports ..................................................................................................................................................................................... 59 5.0 Timer0 Module ........................................................................................................................................................................... 81 6.0 Timer1 Module with Gate Control............................................................................................................................................... 84 7.0 Timer2 Module ........................................................................................................................................................................... 91 8.0 Comparator Module.................................................................................................................................................................... 93 9.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 107 10.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 119 11 ...
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... Wake-up © 2007 Microchip Technology Inc. Block Diagrams and pinout descriptions of the devices are as follows: • PIC16F631 (Figure 1-1, Table 1-1) • PIC16F677 (Figure 1-2, Table 1-2) • PIC16F685 (Figure 1-3, Table 1-3) • PIC16F687/PIC16F689 (Figure 1-4, Table 1-4) • PIC16F690 (Figure 1-5, Table 1-5) ...
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... PIC16F631/677/685/687/689/690 FIGURE 1-2: PIC16F677 BLOCK DIAGRAM Configuration 13 Flash Program Memory Program 14 Bus Instruction Reg 8 Instruction Decode and Start-up Timer Control OSC1/CLKI Timing OSC2/CLKO Generation Internal Oscillator Block MCLR ULPWU T0CKI Ultra Low-Power Timer0 Wake-up AN8 AN9 AN10 AN11 Analog-To-Digital Converter V AN0 AN1 AN2 AN3 AN4 AN5 AN6 ...
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... PIC16F631/677/685/687/689/690 FIGURE 1-3: PIC16F685 BLOCK DIAGRAM Configuration 13 Flash Program Memory Program 14 Bus Instruction Reg 8 Instruction Decode and Control OSC1/CLKI Timing OSC2/CLKO Generation Internal Oscillator Block MCLR T0CKI ULPWU Ultra Low-Power Timer0 Wake-up AN8 AN9 AN10 AN11 Analog-To-Digital Converter V AN0 AN1 AN2 AN3 AN4 AN5 AN6 REF © ...
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... PIC16F631/677/685/687/689/690 FIGURE 1-4: PIC16F687 PIC16F689 BLOCK DIAGRAM / Configuration 13 Flash ( Program 8-Level Stack (13-bit) Memory Program 14 Bus Instruction Reg 8 Instruction Decode and Control Start-up Timer OSC1/CLKI Timing OSC2/CLKO Generation Internal Oscillator Block MCLR T0CKI ULPWU Ultra Low-Power Timer0 Wake-up AN8 AN9 AN10 AN11 ...
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... PIC16F631/677/685/687/689/690 FIGURE 1-5: PIC16F690 BLOCK DIAGRAM Configuration 13 Program Counter Flash Program 8-Level Stack (13-bit) Memory Program 14 Bus Instruction Reg Direct Addr 8 Power-up Instruction Oscillator Decode and Start-up Timer Control OSC1/CLKI Power-on Timing OSC2/CLKO Watchdog Generation Brown-out Internal Oscillator Block MCLR T1G ...
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... PIC16F631/677/685/687/689/690 TABLE 1-1: PINOUT DESCRIPTION – PIC16F631 Name Function RA0/C1IN+/ICSPDAT/ULPWU RA0 C1IN+ ICSPDAT ULPWU RA1/C12IN0-/ICSPCLK RA1 C12IN0- ICSPCLK RA2/T0CKI/INT/C1OUT RA2 T0CKI INT C1OUT RA3/MCLR/V RA3 PP MCLR V PP RA4/T1G/OSC2/CLKOUT RA4 T1G OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN RA5 T1CKI OSC1 CLKIN RB4 RB4 ...
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... PIC16F631/677/685/687/689/690 TABLE 1-1: PINOUT DESCRIPTION – PIC16F631 (CONTINUED) Name Function RC6 RC6 RC7 RC7 Legend Analog input or output TTL = TTL compatible input HV = High Voltage © 2007 Microchip Technology Inc. Input Output Type Type ST CMOS General purpose I/O. ST CMOS General purpose I/O. ...
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... PIC16F631/677/685/687/689/690 TABLE 1-2: PINOUT DESCRIPTION – PIC16F677 Name Function RA0/AN0/C1IN+/ICSPDAT/ RA0 ULPWU AN0 C1IN+ ICSPDAT ULPWU RA1/AN1/C12IN0-/V / RA1 REF ICSPCLK AN1 C12IN0- V REF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA2 AN2 T0CKI INT C1OUT RA3/MCLR/V RA3 PP MCLR V PP RA4/AN3/T1G/OSC2/CLKOUT RA4 AN3 T1G OSC2 CLKOUT ...
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... PIC16F631/677/685/687/689/690 TABLE 1-2: PINOUT DESCRIPTION – PIC16F677 (CONTINUED) Name Function RB7 RB7 RC0/AN4/C2IN+ RC0 AN4 C2IN+ RC1/AN5/C12IN1- RC1 AN5 C12IN1- RC2/AN6/C12IN2- RC2 AN6 C12IN2- RC3/AN7/C12IN3- RC3 AN7 C12IN3- RC4/C2OUT RC4 C2OUT RC5 RC5 RC6/AN8/SS RC6 AN8 SS RC7/AN9/SDO RC7 AN9 SDO Legend: ...
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... PIC16F631/677/685/687/689/690 TABLE 1-3: PINOUT DESCRIPTION – PIC16F685 Name Function RA0/AN0/C1IN+/ICSPDAT/ RA0 ULPWU AN0 C1IN+ ICSPDAT ULPWU RA1/AN1/C12IN0-/V /ICSPCLK RA1 REF AN1 C12IN0- V REF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA2 AN2 T0CKI INT C1OUT RA3/MCLR/V RA3 PP MCLR V PP RA4/AN3/T1G/OSC2/CLKOUT RA4 AN3 T1G OSC2 CLKOUT ...
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... PIC16F631/677/685/687/689/690 TABLE 1-3: PINOUT DESCRIPTION – PIC16F685 (CONTINUED) Name Function RC1/AN5/C12IN1- RC1 AN5 C12IN1- RC2/AN6/C12IN2-/P1D RC2 AN6 C12IN2- P1D RC3/AN7/C12IN3-/P1C RC3 AN7 C12IN3- P1C RC4/C2OUT/P1B RC4 C2OUT P1B RC5/CCP1/P1A RC5 CCP1 P1A RC6/AN8 RC6 AN8 RC7/AN9 RC7 AN9 Legend: ...
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... PIC16F631/677/685/687/689/690 TABLE 1-4: PINOUT DESCRIPTION – PIC16F687/PIC16F689 Name Function RA0/AN0/C1IN+/ICSPDAT/ RA0 ULPWU AN0 C1IN+ ICSPDAT ULPWU RA1/AN1/C12IN0-/V /ICSPCLK RA1 REF AN1 C12IN0- V REF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA2 AN2 T0CKI INT C1OUT RA3/MCLR/V RA3 PP MCLR V PP RA4/AN3/T1G/OSC2/CLKOUT RA4 AN3 T1G OSC2 CLKOUT ...
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... PIC16F631/677/685/687/689/690 TABLE 1-4: PINOUT DESCRIPTION – PIC16F687/PIC16F689 (CONTINUED) Name Function RB6/SCK/SCL RB6 SCK SCL RB7/TX/CK RB7 TX CK RC0/AN4/C2IN+ RC0 AN4 C2IN+ RC1/AN5/C12IN1- RC1 AN5 C12IN1- RC2/AN6/C12IN2- RC2 AN6 C12IN2- RC3/AN7/C12IN3- RC3 AN7 C12IN3- RC4/C2OUT RC4 C2OUT RC5 RC5 RC6/AN8/SS RC6 AN8 ...
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... PIC16F631/677/685/687/689/690 TABLE 1-5: PINOUT DESCRIPTION – PIC16F690 Name Function RA0/AN0/C1IN+/ICSPDAT/ RA0 ULPWU AN0 C1IN+ ICSPDAT ULPWU RA1/AN1/C12IN0-/V /ICSPCLK RA1 REF AN1 C12IN0- V REF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA2 AN2 T0CKI INT C1OUT RA3/MCLR/V RA3 PP MCLR V PP RA4/AN3/T1G/OSC2/CLKOUT RA4 AN3 T1G OSC2 CLKOUT ...
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... PIC16F631/677/685/687/689/690 TABLE 1-5: PINOUT DESCRIPTION – PIC16F690 (CONTINUED) Name Function RB6/SCK/SCL RB6 SCK SCL RB7/TX/CK RB7 TX CK RC0/AN4/C2IN+ RC0 AN4 C2IN+ RC1/AN5/C12IN1- RC1 AN5 C12IN1- RC2/AN6/C12IN2-/P1D RC2 AN6 C12IN2- P1D RC3/AN7/C12IN3-/P1C RC3 AN7 C12IN3- P1C RC4/C2OUT/P1B RC4 C2OUT P1B ...
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... PIC16F631/677/685/687/689/690 NOTES: DS41262D-page 24 © 2007 Microchip Technology Inc. ...
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... Program Memory Organization The PIC16F631/677/685/687/689/690 has a 13-bit program counter capable of addressing program memory space. Only the first (0000h-03FFh) is physically implemented for the PIC16F631, the first (0000h-07FFh) for the PIC16F677/PIC16F687, and the (0000h-0FFFh) for the PIC16F685/PIC16F689/ PIC16F690. Accessing a location above these boundaries will cause a wraparound ...
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... PIC16F631/677/685/687/689/690 FIGURE 2-3: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F677/PIC16F687 PC<12:0> CALL, RETURN 13 RETFIE, RETLW Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory Access 0-7FFh DS41262D-page 26 2.2 Data Memory Organization The data memory (see Figures 2-6 through 2-8) is ...
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... PIC16F631/677/685/687/689/690 FIGURE 2-4: PIC16F631 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC 08h 09h PCLATH 0Ah PCLATH ...
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... PIC16F631/677/685/687/689/690 FIGURE 2-5: PIC16F677 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC 08h 09h PCLATH 0Ah PCLATH ...
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... PIC16F631/677/685/687/689/690 FIGURE 2-6: PIC16F685 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC 08h 09h PCLATH 0Ah PCLATH ...
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... PIC16F631/677/685/687/689/690 FIGURE 2-7: PIC16F687/PIC16F689 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC 08h 09h PCLATH 0Ah PCLATH ...
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... PIC16F631/677/685/687/689/690 FIGURE 2-8: PIC16F690 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC 08h 09h PCLATH 0Ah PCLATH ...
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... PIC16F631/677/685/687/689/690 TABLE 2-1: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module Register 02h PCL Program Counter’s (PC) Least Significant Byte ...
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... PIC16F631/677/685/687/689/690 TABLE 2-2: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RABPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte 83h ...
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... PIC16F631/677/685/687/689/690 TABLE 2-3: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Addr Name Bit 7 Bit 6 Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 101h TMR0 Timer0 Module Register 102h PCL Program Counter’s (PC) Least Significant Byte ...
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... PIC16F631/677/685/687/689/690 TABLE 2-4: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Addr Name Bit 7 Bit 6 Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 181h OPTION_REG RABPU INTEDG 182h PCL Program Counter’s (PC) Least Significant Byte ...
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... PIC16F631/677/685/687/689/690 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (GPR and SFR) The STATUS register can be the destination for any instruction, like any other register. If the STATUS ...
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... PIC16F631/677/685/687/689/690 2.2.2.2 OPTION Register The OPTION register, shown in Register 2- readable and writable register, which contains various control bits to configure: • Timer0/WDT prescaler • External RA2/INT interrupt • Timer0 • Weak pull-ups on PORTA/PORTB REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 RABPU ...
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... PIC16F631/677/685/687/689/690 2.2.2.3 INTCON Register The INTCON register, shown in Register 2- readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/AN2/T0CKI/INT/C1OUT pin interrupts. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 ...
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... PIC16F631/677/685/687/689/690 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 (5) ADIE RCIE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘ ...
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... PIC16F631/677/685/687/689/690 2.2.2.5 PIE2 Register The PIE2 register contains the interrupt enable bits, as shown in Register 2-5. REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 OSFIE C2IE C1IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ...
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... PIC16F631/677/685/687/689/690 2.2.2.6 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-6. REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 U-0 R/W-0 R-0 (5) ADIF RCIF — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘ ...
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... PIC16F631/677/685/687/689/690 2.2.2.7 PIR2 Register The PIR2 register contains the interrupt flag bits, as shown in Register 2-7. REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0 R/W-0 R/W-0 OSFIF C2IF C1IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ...
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... PIC16F631/677/685/687/689/690 2.2.2.8 PCON Register The Power Control (PCON) register (see Register 2-8) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR ...
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... Table Read” (DS00556). DS41262D-page 44 2.3.2 STACK The PIC16F631/677/685/687/689/690 devices have an 8-level x 13-bit wide hardware stack (see Figures 2-2 and 2-3). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... PIC16F631/677/685/687/689/690 FIGURE 2-10: DIRECT/INDIRECT ADDRESSING PIC16F631/677/685/687/689/690 Direct Addressing From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 For memory map detail, see Figures 2-6, 2-7 and 2-8. © 2007 Microchip Technology Inc. 0 IRP Bank Select 180h Bank 1 ...
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... PIC16F631/677/685/687/689/690 NOTES: DS41262D-page 46 © 2007 Microchip Technology Inc. ...
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... PIC16F631/677/685/687/689/690 3.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 3.1 Overview The Oscillator module has a wide variety of clock sources and selection features that allow used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the Oscillator module. ...
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... PIC16F631/677/685/687/689/690 3.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 3-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: • Frequency selection bits (IRCF) • Frequency Status bits (HTS, LTS) • System clock control bits (OSTS, SCS) ...
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... PIC16F631/677/685/687/689/690 3.3 Clock Source Modes Clock Source modes can be classified as external or internal. • External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator mod- ules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. ...
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... PIC16F631/677/685/687/689/690 3.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverter- amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier ...
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... PIC16F631/677/685/687/689/690 3.4.4 EXTERNAL RC MODES The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4 ...
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... PIC16F631/677/685/687/689/690 3.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 ...
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... PIC16F631/677/685/687/689/690 3.5.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 “Frequency Select Bits (IRCF)” ...
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... PIC16F631/677/685/687/689/690 FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC LFINTOSC ≠ 0 IRCF <2:0> System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC LFINTOSC ≠ IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <2:0> ...
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... PIC16F631/677/685/687/689/690 3.6 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit of the OSCCON register. 3.6.1 SYSTEM CLOCK SELECT (SCS) BIT The System Clock Select (SCS) bit of the OSCCON register selects the system clock source that is used for the CPU and peripherals ...
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... PIC16F631/677/685/687/689/690 3.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP ...
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... PIC16F631/677/685/687/689/690 3.8 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word register (CONFIG) ...
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... PIC16F631/677/685/687/689/690 FIGURE 3-9: FSCM TIMING DIAGRAM Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES ...
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... PIC16F631/677/685/687/689/690 4.0 I/O PORTS There are as many as eighteen general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. ...
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... PIC16F631/677/685/687/689/690 4.2 Additional Pin Functions Every PORTA pin on this device family has an interrupt-on-change option and a weak pull-up option. RA0 also has an Ultra Low-Power Wake-up option. The next three sections describe these functions. 4.2.1 ANSEL AND ANSELH REGISTERS The ANSEL and ANSELH registers are used to disable ...
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... PIC16F631/677/685/687/689/690 REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 ANS7 ANS6 ANS5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively Analog input. Pin is assigned as analog input 0 = Digital I/O ...
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... PIC16F631/677/685/687/689/690 REGISTER 4-5: WPUA: PORTA REGISTER U-0 U-0 R/W-1 — — WPUA5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPUA<5:4>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘ ...
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... PIC16F631/677/685/687/689/690 4.2.4 ULTRA LOW-POWER WAKE-UP The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt-on-change on RA0 without excess current consumption. The mode is selected by setting the ULPWUE bit of the PCON register. This enables a small current sink, which can be used to discharge a capacitor on RA0. ...
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... Figure 4-2 shows the diagram for this pin. The RA0/AN0/C1IN+/ICSPDAT/ULPWU pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC (except PIC16F631) • an analog input to Comparator C1 • In-Circuit Serial Programming™ data • an analog input for the Ultra Low-Power Wake-up ...
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... Figure 4-3 shows the diagram for this pin. The RA2/AN2/T0CKI/INT/C1OUT pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC (except PIC16F631) • the clock input for TMR0 • an external edge triggered interrupt • a digital output from Comparator C1 ...
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... RA4/AN3/T1G/OSC2/CLKOUT Figure 4-5 shows the diagram for this pin. The RA4/AN3/T1G/OSC2/CLKOUT pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC (except PIC16F631) • a TMR1 gate input • a crystal/resonator connection • a clock output V DD ...
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... PIC16F631/677/685/687/689/690 4.2.5.6 RA5/T1CKI/OSC1/CLKIN Figure 4-6 shows the diagram for this pin. The RA5/T1CKI/OSC1/CLKIN pin is configurable function as one of the following: • a general purpose I/O • a TMR1 clock input • a crystal/resonator connection • a clock input FIGURE 4-6: BLOCK DIAGRAM OF RA5 INTOSC Mode TMR1LPEN ...
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... PIC16F631/677/685/687/689/690 TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 Bit 5 ADCON0 ADFM VCFG CHS3 ANSEL ANS7 ANS6 ANS5 CM1CON0 C1ON C1OUT C1OE INTCON GIE PEIE T0IE IOCA — — IOCA5 OPTION_REG RABPU INTEDG T0CS PORTA — — RA5 SSPCON ...
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... PIC16F631/677/685/687/689/690 4.3 PORTB and TRISB Registers PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 4-6). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
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... PIC16F631/677/685/687/689/690 REGISTER 4-8: TRISB: PORTB TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 TRISB7 TRISB6 TRISB5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 TRISB<7:4>: PORTB Tri-State Control bit 1 = PORTB pin configured as an input (tri-stated PORTB pin configured as an output bit 3-0 Unimplemented: Read as ‘ ...
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... RB4/AN10/SDI/SDA Figure 4-7 shows the diagram for this pin. The (1) RB4/AN10/SDI/SDA pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC (except PIC16F631) • a SPI data I/O 2 • data I/O Note 1: SDI and SDA are PIC16F687/PIC16F689/PIC16F690 only ...
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... Figure 4-8 shows the diagram for this pin. The (1,2) RB5/AN11/RX/DT pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC (except PIC16F631) • an asynchronous serial input • a synchronous serial data I/O Note 1: RX and DT are PIC16F687/PIC16F689/PIC16F690 only ...
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... PIC16F631/677/685/687/689/690 4.4.3.3 RB6/SCK/SCL Figure 4-9 shows the diagram for this pin. The (1) RB6/SCK/SCL pin is configurable to function as one of the following: • a general purpose I/O • a SPI clock 2 • C™ clock Note 1: SCK and SCL are PIC16F677/PIC16F687/PIC16F689/ PIC16F690 only. © 2007 Microchip Technology Inc. ...
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... PIC16F631/677/685/687/689/690 4.4.3.4 RB7/TX/CK Figure 4-10 shows the diagram for this pin. The (1) RB7/TX/CK pin is configurable to function as one of the following: • a general purpose I/O • an asynchronous serial output • a synchronous clock I/O Note 1: TX and CK are PIC16F687/PIC16F689/PIC16F690 only. DS41262D-page 74 FIGURE 4-10: Data Bus ...
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... PIC16F631/677/685/687/689/690 TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 Bit 5 IOCB IOCB7 IOCB6 IOCB5 INTCON GIE PEIE T0IE PORTB RB7 RB6 RB5 TRISB TRISB7 TRISB6 TRISB5 TRISB4 WPUB WPUB7 WPUB6 WPUB5 WPUB4 Legend unknown unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by PORTB. ...
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... PIC16F631/677/685/687/689/690 4.5 PORTC and TRISC Registers PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 4-10). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...
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... Not implemented on PIC16F631. © 2007 Microchip Technology Inc. 4.5.3 RC2/AN6/C12IN2-/P1D The RC2/AN6/P1D one of the following: • a general purpose I/O • an analog input for the ADC (except PIC16F631) • a PWM output • an analog input to Comparator Note 1: P1D is available on PIC16F685/PIC16F690 only. 4.5.4 RC3/AN7/C12IN3-/P1C ...
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... PIC16F631/677/685/687/689/690 4.5.5 RC4/C2OUT/P1B (1, 2) The RC4/C2OUT/P1B is configurable to function as one of the following: • a general purpose I/O • a digital output from Comparator C2 • a PWM output Note 1: Enabling both C2OUT and P1B will cause a conflict on RC4 and create unpredictable results. Therefore, if C2OUT is enabled, the ECCP+ can not be used in Half-Bridge or Full-Bridge mode and vise-versa ...
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... PIC16F631/677/685/687/689/690 4.5.7 RC6/AN8/SS (1,2) The RC6/AN8/SS is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC (except PIC16F631) • a slave select input SS Note 1: is available on PIC16F687/PIC16F689/PIC16F690 only. 2: AN8 is not implemented on PIC16F631. FIGURE 4-15: BLOCK DIAGRAM OF RC6 ...
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... PIC16F631/677/685/687/689/690 TABLE 4-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 Bit 5 ANSEL ANS7 ANS6 ANS5 ANSELH — — — (2) CCP1CON P1M1 P1M0 DC1B1 CM2CON0 C2ON C2OUT C2OE CM2CON1 MC1OUT MC2OUT — PORTC RC7 RC6 RC5 PSTRCON — — — SRCON ...
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... PIC16F631/677/685/687/689/690 5.0 TIMER0 MODULE The Timer0 module is an 8-bit timer/counter with the following features: • 8-bit timer/counter register (TMR0) • 8-bit prescaler (shared with Watchdog Timer) • Programmable internal or external clock source • Programmable external clock edge selection • Interrupt on overflow Figure 5 block diagram of the Timer0 module ...
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... PIC16F631/677/685/687/689/690 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. ...
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... PIC16F631/677/685/687/689/690 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 RABPU INTEDG T0CS bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RABPU: PORTA/PORTB Pull-up Enable bit 1 = PORTA/PORTB pull-ups are disabled 0 = PORTA/PORTB pull-ups are enabled by individual PORT latch values ...
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... PIC16F631/677/685/687/689/690 6.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 3-bit prescaler • Optional LP oscillator • Synchronous or asynchronous operation • Timer1 gate (count enable) via comparator or T1G pin • ...
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... PIC16F631/677/685/687/689/690 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples determined by the Timer1 prescaler. OSC 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. ...
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... PIC16F631/677/685/687/689/690 Note: TMR1GE bit of the T1CON register must be set to use either T1G or C2OUT as the Timer1 gate source. See the CM2CON1 register (Register 8-3) for more informa- tion on selecting the Timer1 gate source. Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or Comparator C2 output ...
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... PIC16F631/677/685/687/689/690 FIGURE 6-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2007 Microchip Technology Inc. DS41262D-page 87 ...
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... PIC16F631/677/685/687/689/690 6.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 6-1: T1CON: TIMER 1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 (1) (2) T1GINV TMR1GE T1CKPS1 bit 7 Legend Readable bit ...
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... PIC16F631/677/685/687/689/690 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 CM2CON1 MC1OUT MC2OUT — INTCON GIE PEIE T0IE PIE1 — ADIE RCIE PIR1 — ADIF RCIF TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1L ...
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... PIC16F631/677/685/687/689/690 NOTES: DS41262D-page 90 © 2007 Microchip Technology Inc. ...
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... PIC16F631/677/685/687/689/690 7.0 TIMER2 MODULE The Timer2 module is an eight-bit timer with the following features: • 8-bit timer register (TMR2) • 8-bit period register (PR2) • Interrupt on TMR2 match with PR2 • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) See Figure 7-1 for a block diagram of Timer2 ...
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... PIC16F631/677/685/687/689/690 REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler ...
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... PIC16F631/677/685/687/689/690 8.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The Analog Comparator module includes the following features: • ...
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... PIC16F631/677/685/687/689/690 FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> 2 C12IN0- 0 C12IN1- 1 MUX C12IN2- 2 C12IN3- 3 C1R C1IN+ 0 MUX FixedRef 1 0 MUX CV REF 1 Note 1: 2: C1V REN 3: FIGURE 8-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM C2CH<1:0> 2 C12IN0- 0 C12IN1- 1 C2V MUX C2IN2- 2 C2V C2IN3- 3 C2R C2IN+ 0 MUX ...
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... PIC16F631/677/685/687/689/690 8.2 Comparator Control Each comparator has a separate Configuration register: CM1CON0 for Comparator C1 and CM2CON0 for Comparator C2. In addition, Comparator C2 has a second control register, CM2CON1, for controlling the interaction with Timer1 and simultaneous reading of both comparator outputs. The CM1CON0 and CM2CON0 registers (see Registers ...
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... PIC16F631/677/685/687/689/690 8.4 Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusive- or gate (see Figure 8-2 and Figure 8-3). One latch is updated with the comparator output level when the CMxCON0 register is read ...
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... PIC16F631/677/685/687/689/690 8.5 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 17.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator ...
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... PIC16F631/677/685/687/689/690 REGISTER 8-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 C1ON C1OUT C1OE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit ...
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... PIC16F631/677/685/687/689/690 REGISTER 8-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 C2ON C2OUT C2OE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 C2ON: Comparator C2 Enable bit 1 = Comparator C2 is enabled 0 = Comparator C2 is disabled bit 6 C2OUT: Comparator C2 Output bit ...
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... PIC16F631/677/685/687/689/690 8.7 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 8-6. Since the analog input pins share their con- nection with a digital input, they have reverse biased ESD protection diodes to V and V DD input, therefore, must be between V SS input voltage deviates from this range by more than 0 ...
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... PIC16F631/677/685/687/689/690 8.8 Additional Comparator Features There are three additional comparator features: • Timer1 count enable (gate) • Synchronizing output with Timer1 • Simultaneous read of comparator outputs 8.8.1 COMPARATOR C2 GATING TIMER1 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CM2CON1 register will enable Timer1 to increment based on the output of Comparator C2 ...
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... PIC16F631/677/685/687/689/690 8.9 Comparator SR Latch The SR Latch module provides additional control of the comparator outputs. The module consists of a single SR latch and output multiplexers. The SR latch can be set, reset or toggled by the comparator outputs. The SR latch may also be set or reset, independent of comparator output, by control bits in the SRCON control register ...
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... PIC16F631/677/685/687/689/690 REGISTER 8-4: SRCON: SR LATCH CONTROL REGISTER R/W-0 R/W-0 R/W-0 (2) (2) SR1 SR0 C1SEN bit 7 Legend Bit is set only R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SR1: SR Latch Configuration bit 1 = C2OUT pin is the latch Q output 0 = C2OUT pin is the C2 comparator output ...
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... PIC16F631/677/685/687/689/690 8.10 Comparator Voltage Reference The comparator voltage reference module provides an internally generated voltage reference for the compara- tors. The following features are available: • Independent from Comparator operation • Two 16-level voltage ranges • Output clamped • Ratiometric with V DD • ...
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... PIC16F631/677/685/687/689/690 8.10.5 FIXED VOLTAGE REFERENCE The fixed voltage reference is independent nominal output voltage of 0.6V. This reference can be enabled by setting the VP6EN bit of the VRCON register to ‘1’. This reference is always enabled when the HFINTOSC oscillator is active. 8.10.6 FIXED VOLTAGE REFERENCE STABILIZATION PERIOD ...
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... PIC16F631/677/685/687/689/690 REGISTER 8-5: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 C1VREN C2VREN VRR bit 7 Legend Bit is set only R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 C1VREN: Comparator C1 Voltage Reference Enable bit circuit powered on and routed to C1V REF ...
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... PIC16F631/677/685/687/689/690 9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter ...
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... PIC16F631/677/685/687/689/690 9.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Results formatting 9.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...
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... PIC16F631/677/685/687/689/690 TABLE 9-1: ADC CLOCK PERIOD (T ADC Clock Period ( ADC Clock Source ADCS<2:0> 000 OSC F /4 100 OSC F /8 001 OSC F /16 101 OSC F /32 OSC 010 F /64 OSC 110 F x11 RC Legend: Shaded cells are outside of recommended range. Note 1: The F source has a typical T ...
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... PIC16F631/677/685/687/689/690 9.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 9-3 shows the two output formats. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT ...
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... PIC16F631/677/685/687/689/690 9.2 ADC Operation 9.2.1 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 9.2.6 “ ...
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... PIC16F631/677/685/687/689/690 EXAMPLE 9-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B’01110000’ ;ADC Frc clock MOVWF ADCON1 ; BANKSEL TRISA ; BSF TRISA,0 ...
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... PIC16F631/677/685/687/689/690 REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 ADFM VCFG CHS3 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit ...
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... PIC16F631/677/685/687/689/690 REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 — ADCS2 ADCS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = F /2 OSC ...
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... PIC16F631/677/685/687/689/690 REGISTER 9-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 9-4: ...
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... PIC16F631/677/685/687/689/690 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (C ) must be allowed to fully HOLD charge to the input channel voltage level. The Analog Input model is shown in Figure 9-4. The source impedance (R ) and the internal sampling switch (R ...
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... PIC16F631/677/685/687/689/690 FIGURE 9-4: ANALOG INPUT MODEL ANx Rs C PIN Legend Input Capacitance PIN V = Threshold Voltage Leakage current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance HOLD FIGURE 9-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 004h ...
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... PIC16F631/677/685/687/689/690 TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Name Bit 7 Bit 6 Bit 5 ADCON0 ADFM VCFG CHS3 ADCON1 — ADCS2 ADCS1 ANSEL ANS7 ANS6 ANS5 ANSELH — — — ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte INTCON GIE ...
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... EEDAT location being accessed. These devices, except for the PIC16F631, have 256 bytes of data EEPROM with an address range from 0h to 0FFh. The PIC16F631 has 128 bytes of data EEPROM with an address range from 0h to 07Fh. When accessing the program memory block of the ...
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... PIC16F631/677/685/687/689/690 REGISTER 10-1: EEDAT: EEPROM DATA REGISTER R/W-0 R/W-0 R/W-0 EEDAT7 EEDAT6 EEDAT5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 EEDAT<7:0>: 8 Least Significant Address bits to Write to or Read from data EEPROM or Read from program memory ...
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... PIC16F631/677/685/687/689/690 REGISTER 10-5: EECON1: EEPROM CONTROL REGISTER R/W-x U-0 U-0 (1) EEPGD — — bit 7 Legend Bit can only be set R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory bit 6-4 Unimplemented: Read as ‘ ...
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... PIC16F631/677/685/687/689/690 10.1.2 READING THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register, and then set control bit RD. The data is available at the very next cycle, in the EEDAT register; therefore, it can be read in the next instruction ...
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... PIC16F631/677/685/687/689/690 10.1.4 READING THE FLASH PROGRAM MEMORY (PIC16F685/PIC16F689/ PIC16F690) To read a program memory location, the user must write the Least and Most Significant address bits to the EEADR and EEADRH registers, set the EEPGD con- trol bit of the EECON1 register, and then set control bit RD ...
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... PIC16F631/677/685/687/689/690 FIGURE 10-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDAT Register EERHLT DS41262D-page 124 EEADRH,EEADR PC+3 INSTR ( EEDATH,EEDAT INSTR ( INSTR( Forced NOP executed here executed here INSTR ( ...
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... PIC16F631/677/685/687/689/690 10.2 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 10-4) to the desired value to be written. EXAMPLE 10-4: WRITE VERIFY BANKSEL EEDAT ; MOVF EEDAT, W ;EEDAT not changed ;from previous write BANKSEL EECON1 ...
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... PIC16F631/677/685/687/689/690 TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Name Bit 7 Bit 6 Bit 5 (1) EECON1 EEPGD — — EECON2 EEPROM Control Register 2 (not a physical register) (2) EEADR EEADR7 EEADR6 EEADR5 (1) EEADRH — — — EEDAT EEDAT7 EEDAT6 EEDAT5 (1) EEDATH — — EEDATH5 ...
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... PIC16F631/677/685/687/689/690 11.0 ENHANCED CAPTURE/COMPARE/PWM MODULE The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired ...
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... PIC16F631/677/685/687/689/690 11.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • Every falling edge • Every rising edge • Every 4th rising edge • ...
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... PIC16F631/677/685/687/689/690 11.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP module may: • Toggle the CCP1 output • Set the CCP1 output • Clear the CCP1 output • ...
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... PIC16F631/677/685/687/689/690 11.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • PR2 • T2CON • CCPR1L • CCP1CON In Pulse-Width Modulation (PWM) mode, the CCP module produces 10-bit resolution PWM output on the CCP1 pin ...
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... PIC16F631/677/685/687/689/690 11.3.1 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 11-1. EQUATION 11-1: PWM PERIOD [ ( ) ] 4 T • • PWM Period = PR2 + 1 (TMR2 Prescale Value) When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • ...
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... PIC16F631/677/685/687/689/690 11.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. ...
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... PIC16F631/677/685/687/689/690 11.4 PWM (Enhanced Mode) The Enhanced PWM Mode can generate a PWM signal four different output pins with up to 10-bits of resolution. It can do this through four different PWM Output modes: • Single PWM • Half-Bridge PWM • Full-Bridge PWM, Forward mode • Full-Bridge PWM, Reverse mode To select an Enhanced PWM mode, the P1M bits of the CCP1CON register must be set appropriately ...
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... PIC16F631/677/685/687/689/690 FIGURE 11-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Signal P1M<1:0> P1A Modulated (Single Output) 00 P1A Modulated (Half-Bridge) 10 P1B Modulated P1A Active P1B Inactive (Full-Bridge, 01 Forward) P1C Inactive P1D Modulated P1A Inactive P1B Modulated (Full-Bridge, 11 Reverse) P1C Active P1D Inactive Relationships: • ...
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... PIC16F631/677/685/687/689/690 FIGURE 11-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal P1M<1:0> (Single Output) P1A Modulated 00 P1A Modulated (Half-Bridge) 10 P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive P1B Modulated (Full-Bridge, 11 Reverse) P1C Active P1D Inactive Relationships: • ...
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... PIC16F631/677/685/687/689/690 11.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 11-6). This mode can be used for Half-Bridge ...
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... PIC16F631/677/685/687/689/690 11.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 11-10. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure 11-11. ...
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... PIC16F631/677/685/687/689/690 FIGURE 11-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode (2) P1A Pulse Width (2) P1B (2) P1C (2) P1D (1) Reverse Mode Pulse Width (2) P1A (2) P1B (2) P1C (2) P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS41262D-page 138 Period ...
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... PIC16F631/677/685/687/689/690 11.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. ...
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... PIC16F631/677/685/687/689/690 FIGURE 11-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE P1A P1B P1C P1D External Switch C External Switch D Potential Shoot-Through Current Note 1: All signals are shown as active-high the turn on delay of power switch QC and its driver the turn off delay of power switch QD and its driver. ...
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... PIC16F631/677/685/687/689/690 11.4.4 ENHANCED PWM AUTO-SHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application ...
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... PIC16F631/677/685/687/689/690 Note 1: The auto-shutdown condition level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period ...
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... PIC16F631/677/685/687/689/690 11.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off ...
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... PIC16F631/677/685/687/689/690 REGISTER 11-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away ...
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... PIC16F631/677/685/687/689/690 11.4.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode (CCP1M<3:2> and P1M<1:0> CCP1CON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STR< ...
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... PIC16F631/677/685/687/689/690 FIGURE 11-18: SIMPLIFIED STEERING BLOCK DIAGRAM STRA P1A Signal CCP1M1 1 PORT Data 0 TRIS STRB CCP1M0 1 PORT Data 0 TRIS STRC 1 CCP1M1 PORT Data 0 TRIS STRD CCP1M0 1 PORT Data 0 TRIS Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0> and CCP1M< ...
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... PIC16F631/677/685/687/689/690 11.4.7.1 Steering Synchronization The STRSYNC bit of the PSTRCON register gives the user two selections of when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRCON register. In this case, the output signal at the P1< ...
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... PIC16F631/677/685/687/689/690 TABLE 11-5: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND PWM Name Bit 7 Bit 6 Bit 5 CCP1CON P1M1 P1M0 DC1B1 CM1CON0 C1ON C1OUT C1OE CM2CON0 C2ON C2OUT C2OE CM2CON1 MC1OUT MC2OUT — CCPR1L Capture/Compare/PWM Register 1 Low Byte CCPR1H Capture/Compare/PWM Register 1 High Byte ...
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... PIC16F631/677/685/687/689/690 12.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The ...
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... PIC16F631/677/685/687/689/690 FIGURE 12-2: EUSART RECEIVE BLOCK DIAGRAM RX/DT pin Pin Buffer and Control Baud Rate Generator BRG16 + 1 Multiplier SYNC SPBRGH SPBRG BRGH BRG16 The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • ...
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... PIC16F631/677/685/687/689/690 12.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels mark state which OH represents a ‘1’ data bit, and a V space state which OL represents a ‘0’ data bit. NRZ refers to the fact that ...
Page 154
... PIC16F631/677/685/687/689/690 12.1.1.4 TSR Status The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register ...
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... PIC16F631/677/685/687/689/690 TABLE 12-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Name Bit 7 Bit 6 Bit 5 BAUDCTL ABDOVF RCIDL — INTCON GIE PEIE T0IE PIE1 — ADIE RCIE PIR1 — ADIF RCIF RCREG EUSART Receive Data Register RCSTA SPEN RX9 SREN SPBRG BRG7 BRG6 BRG5 ...
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... PIC16F631/677/685/687/689/690 12.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 12-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate ...
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... PIC16F631/677/685/687/689/690 12.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO ...
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... PIC16F631/677/685/687/689/690 12.1.2.8 Asynchronous Reception Set-up: 1. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 12.3 “EUSART Baud Rate Generator (BRG)”). 2. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation ...
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... PIC16F631/677/685/687/689/690 TABLE 12-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 Bit 5 BAUDCTL ABDOVF RCIDL — INTCON GIE PEIE T0IE PIE1 — ADIE RCIE PIR1 — ADIF RCIF RCREG EUSART Receive Data Register RCSTA SPEN RX9 SREN SPBRG BRG7 BRG6 BRG5 ...
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... PIC16F631/677/685/687/689/690 12.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block out- put (INTOSC). However, the INTOSC frequency may drift temperature changes, and this directly DD affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind ...
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... PIC16F631/677/685/687/689/690 REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 SPEN RX9 SREN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) ...
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... PIC16F631/677/685/687/689/690 REGISTER 12-3: BAUDCTL: BAUD RATE CONTROL REGISTER R-0 R-1 U-0 ABDOVF RCIDL — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’ ...
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... PIC16F631/677/685/687/689/690 12.3 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCTL register selects 16-bit mode ...
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... PIC16F631/677/685/687/689/690 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES F = 20.000 MHz OSC BAUD SPBRG RATE Actual % Actual value Rate Error (decimal) 300 — — — 1200 1221 1.73 255 2400 2404 0.16 129 9600 9470 -1.36 32 10417 10417 0.00 29 10286 19.2k 19.53k 1 ...
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... PIC16F631/677/685/687/689/690 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED 4.000 MHz OSC BAUD SPBRG RATE Actual % Actual value Rate Error (decimal) 300 — — — 1200 1202 0.16 207 2400 2404 0.16 103 9600 9615 0.16 25 10417 10417 0.00 23 19.2k 19.23k ...
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... PIC16F631/677/685/687/689/690 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 20.000 MHz OSC BAUD SPBRG RATE Actual % Actual value Rate Error (decimal) 300 300.0 0.00 16665 1200 1200 -0.01 4166 2400 2400 0.02 2082 9600 9597 -0 ...
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... PIC16F631/677/685/687/689/690 12.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “ ...
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... PIC16F631/677/685/687/689/690 12.3.2 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. ...
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... PIC16F631/677/685/687/689/690 FIGURE 12-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Bit Set by User WUE bit RX/DT Line RCIF Sleep Command Executed Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active ...
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... PIC16F631/677/685/687/689/690 FIGURE 12-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit TXIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB SENDB (send Break control bit) DS41262D-page 168 bit 0 bit 1 bit 11 ...
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... PIC16F631/677/685/687/689/690 12.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary cir- cuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry ...
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... PIC16F631/677/685/687/689/690 FIGURE 12-10: SYNCHRONOUS TRANSMISSION RX/DT bit 0 bit 1 pin Word 1 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ TXEN bit Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. ...
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... PIC16F631/677/685/687/689/690 12.4.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register) ...
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... PIC16F631/677/685/687/689/690 FIGURE 12-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT bit 0 pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit ‘0’ CREN bit RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. ...
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... PIC16F631/677/685/687/689/690 12.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • SYNC = 1 • CSRC = 0 • SREN = 0 (for transmit); SREN = 1 (for receive) • CREN = 0 (for transmit); CREN = 1 (for receive) • SPEN = 1 Setting the SYNC bit of the TXSTA register configures the device for synchronous operation ...
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... PIC16F631/677/685/687/689/690 12.4.2.3 EUSART Synchronous Slave Reception The operation of the Synchronous Master and Slave modes is identical (Section 12.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don't care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep ...
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... PIC16F631/677/685/687/689/690 13.0 SSP MODULE OVERVIEW The Synchronous Serial Port (SSP) module is a serial interface used to communicate with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: • ...
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... PIC16F631/677/685/687/689/690 REGISTER 13-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER R/W-0 R/W-0 R-0 SMP CKE D/A bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode Input data sampled at end of data output time ...
Page 179
... PIC16F631/677/685/687/689/690 REGISTER 13-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) ...
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... PIC16F631/677/685/687/689/690 13.2 Operation When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
Page 181
... PIC16F631/677/685/687/689/690 13.3 Enabling SPI I/O To enable the serial port, SSP Enable bit SSPEN of the SSPCON register must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins ...
Page 182
... PIC16F631/677/685/687/689/690 13.5 Master Mode The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 13- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input) ...
Page 183
... PIC16F631/677/685/687/689/690 13.6 Slave Mode In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications ...
Page 184
... PIC16F631/677/685/687/689/690 FIGURE 13-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 13-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
Page 185
... PIC16F631/677/685/687/689/690 13.8 Sleep Operation In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to Normal mode, the module will continue to transmit/ receive data. In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device ...
Page 186
... PIC16F631/677/685/687/689/690 2 13.11 SSP I C Operation 2 The SSP module mode, fully implements all slave functions, except general call support, and provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the Standard specifications, as well as 7-bit and 10-bit addressing. ...
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... PIC16F631/677/685/687/689/690 13.12.1 ADDRESSING Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register ...
Page 188
... PIC16F631/677/685/687/689/690 13.12.2 RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow ...
Page 189
... PIC16F631/677/685/687/689/690 13.12.3 SSP MASK REGISTER An SSP Mask (SSPMSK) register is available in I Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK register has the effect of making the corresponding bit in the SSPSR register a ‘ ...
Page 190
... PIC16F631/677/685/687/689/690 2 FIGURE 13-9: I C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS) DS41262D-page 188 © 2007 Microchip Technology Inc. ...
Page 191
... PIC16F631/677/685/687/689/690 13.12.4 TRANSMISSION When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RB6/SCK/SCL is held low ...
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... PIC16F631/677/685/687/689/690 2 I FIGURE 13-11: C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) DS41262D-page 190 © 2007 Microchip Technology Inc. ...
Page 193
... PIC16F631/677/685/687/689/690 13.13 Master Mode Master mode of operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the ...
Page 194
... PIC16F631/677/685/687/689/690 FIGURE 13-12: CLOCK SYNCHRONIZATION TIMING SDA DX SCL CKP WR SSPCON TABLE 13-4: REGISTERS ASSOCIATED WITH I Addr Name Bit 7 Bit 6 0Bh/8Bh/ INTCON GIE PEIE 10Bh/18Bh 0Ch PIR1 — ADIF 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 14h SSPCON WCOL SSPOV 86h ...
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... PIC16F631/677/685/687/689/690 14.0 SPECIAL FEATURES OF THE CPU The PIC16F631/677/685/687/689/690 have a host of features intended to maximize system reliability, minimize cost through elimination of external compo- nents, provide power saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) ...
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... PIC16F631/677/685/687/689/690 14.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 14-2. These bits are mapped in program memory location 2007h. Note: Address 2007h is beyond the user program memory space. It belongs to the special ...
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... PIC16F631/677/685/687/689/690 REGISTER 14-1: CONFIG: CONFIGURATION WORD REGISTER Reserved Reserved bit 13 (3) (4) CP MCLRE bit 6 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 13-12 Reserved: Reserved bits. Do Not Use. bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled ...
Page 198
... PIC16F631/677/685/687/689/690 14.2 Reset The PIC16F631/677/685/687/689/690 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Reset (BOR) Some registers are not affected in any Reset condition; ...
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... For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 14.2.2 MCLR PIC16F631/677/685/687/689/690 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...
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... PIC16F631/677/685/687/689/690 14.2.4 BROWN-OUT RESET (BOR) The BOREN0 and BOREN1 bits in the Configuration Word register select one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable. When BOREN<1:0> = 01, the SBOREN bit (PCON<4>) enables/disables the BOR allowing controlled in software. By selecting BOREN< ...