PIC16F631-I/P Microchip Technology Inc., PIC16F631-I/P Datasheet - Page 188
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PIC16F631-I/P
Manufacturer Part Number
PIC16F631-I/P
Description
MCU, 8-Bit, 1KW Flash, 64 RAM, 18 I/O, PDIP-20
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F631-IP.pdf
(294 pages)
Specifications of PIC16F631-I/P
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
128 Bytes
Input Output
18
Memory Type
Flash
Number Of Bits
8
Package Type
20-pin PDIP
Programmable Memory
1.75K Bytes
Ram Size
64 Bytes
Speed
20 MHz
Timers
1-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F631-I/P
Manufacturer:
MICROCHIP
Quantity:
4 500
Part Number:
PIC16F631-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC16F631/677/685/687/689/690
13.12.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF of the SSPSTAT
register is set, or bit SSPOV of the SSPCON register is
set. This is an error condition due to the user’s firm-
ware.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF of the PIR1 register must be
cleared in software. The SSPSTAT register is used to
determine the status of the byte.
FIGURE 13-8:
DS41262D-page 186
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S
RECEPTION
A7 A6 A5 A4 A3 A2 A1
1
2
Receiving Address
3
4
I
2
C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
5
6
7
R/W = 0
8
ACK
9
D7
1
D6
2
SSPBUF register is read
Receiving Data
D5
3
Cleared in software
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
D1
7
D0
8
ACK
9
D7
1
D6
2
D5
Receiving Data
3
D4
4
© 2007 Microchip Technology Inc.
ACK is not sent.
D3
5
D2
6
D1
7
D0
8
ACK
9
transfer
Bus Master
terminates
P
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