PIC16F631-I/P Microchip Technology Inc., PIC16F631-I/P Datasheet - Page 28
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PIC16F631-I/P
Manufacturer Part Number
PIC16F631-I/P
Description
MCU, 8-Bit, 1KW Flash, 64 RAM, 18 I/O, PDIP-20
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F631-IP.pdf
(294 pages)
Specifications of PIC16F631-I/P
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
128 Bytes
Input Output
18
Memory Type
Flash
Number Of Bits
8
Package Type
20-pin PDIP
Programmable Memory
1.75K Bytes
Ram Size
64 Bytes
Speed
20 MHz
Timers
1-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F631-I/P
Manufacturer:
MICROCHIP
Quantity:
4 500
Part Number:
PIC16F631-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC16F631/677/685/687/689/690
FIGURE 2-3:
DS41262D-page 26
CALL, RETURN
RETFIE, RETLW
On-chip Program
Interrupt Vector
Stack Level 1
Stack Level 2
Stack Level 8
Access 0-7FFh
Reset Vector
PC<12:0>
Memory
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F677/PIC16F687
13
0000h
0004h
0005h
07FFh
0800h
1FFFh
2.2
The data memory (see Figures 2-6 through 2-8) is
partitioned into four banks which contain the General
Purpose Registers (GPR) and the Special Function
Registers (SFR). The Special Function Registers are
located in the first 32 locations of each bank. The
General Purpose Registers, implemented as static
RAM, are located in the last 96 locations of each Bank.
Register locations F0h-FFh in Bank 1, 170h-17Fh in
Bank 2 and 1F0h-1FFh in Bank 3 point to addresses
70h-7Fh in Bank 0. The actual number of General
Purpose Resisters (GPR) in each Bank depends on the
device. Details are shown in Figures 2-4 through 2-8.
All other RAM is unimplemented and returns ‘0’ when
read. RP<1:0> of the STATUS register are the bank
select bits:
RP1
2.2.1
The register file is organized as 128 x 8 in the
PIC16F687
PIC16F685/PIC16F689/PIC16F690. Each register is
accessed, either directly or indirectly, through the File
Select Register (FSR) (see Section 2.4 “Indirect
Addressing, INDF and FSR Registers”).
2.2.2
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1
through 2-4). These registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Registers related to the operation of peripheral features
are described in the section of that peripheral feature.
0
0
1
1
RP0
0
1
0
1
Data Memory Organization
GENERAL PURPOSE REGISTER
FILE
SPECIAL FUNCTION REGISTERS
→
→
→
→
and
Bank 0 is selected
Bank 1 is selected
Bank 2 is selected
Bank 3 is selected
© 2007 Microchip Technology Inc.
256
x
8
in
the
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