PIC16F631-I/P Microchip Technology Inc., PIC16F631-I/P Datasheet - Page 40
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PIC16F631-I/P
Manufacturer Part Number
PIC16F631-I/P
Description
MCU, 8-Bit, 1KW Flash, 64 RAM, 18 I/O, PDIP-20
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F631-IP.pdf
(294 pages)
Specifications of PIC16F631-I/P
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
128 Bytes
Input Output
18
Memory Type
Flash
Number Of Bits
8
Package Type
20-pin PDIP
Programmable Memory
1.75K Bytes
Ram Size
64 Bytes
Speed
20 MHz
Timers
1-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F631-I/P
Manufacturer:
MICROCHIP
Quantity:
4 500
Part Number:
PIC16F631-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC16F631/677/685/687/689/690
2.2.2.3
The INTCON register, shown in Register 2-3, is a
readable and writable register, which contains the various
enable and flag bits for TMR0 register overflow, PORTA
change and external RA2/AN2/T0CKI/INT/C1OUT pin
interrupts.
REGISTER 2-3:
DS41262D-page 38
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
GIE
2:
3:
IOCA or IOCB register must also be enabled.
T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
Includes ULPWU interrupt.
INTCON Register
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
RABIE: PORTA/PORTB Change Interrupt Enable bit
1 = Enables the PORTA/PORTB change interrupt
0 = Disables the PORTA/PORTB change interrupt
T0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
RABIF: PORTA/PORTB Change Interrupt Flag bit
1 = When at least one of the PORTA or PORTB general purpose I/O pins changed state (must be
0 = None of the PORTA or PORTB general purpose I/O pins have changed state
R/W-0
PEIE
cleared in software)
INTCON: INTERRUPT CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
T0IE
R/W-0
INTE
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RABIE
R/W-0
Note:
(1,3)
(1,3)
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
T0IF
R/W-0
(2)
software
© 2007 Microchip Technology Inc.
x = Bit is unknown
R/W-0
INTF
should
ensure
RABIF
R/W-x
bit 0
the
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