PIC16F631-I/P Microchip Technology Inc., PIC16F631-I/P Datasheet - Page 290
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PIC16F631-I/P
Manufacturer Part Number
PIC16F631-I/P
Description
MCU, 8-Bit, 1KW Flash, 64 RAM, 18 I/O, PDIP-20
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F631-IP.pdf
(294 pages)
Specifications of PIC16F631-I/P
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
128 Bytes
Input Output
18
Memory Type
Flash
Number Of Bits
8
Package Type
20-pin PDIP
Programmable Memory
1.75K Bytes
Ram Size
64 Bytes
Speed
20 MHz
Timers
1-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F631-I/P
Manufacturer:
MICROCHIP
Quantity:
4 500
Part Number:
PIC16F631-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16F631/677/685/687/689/690
Timer2
Timers
Timing Diagrams
DS41262D-page 288
Associated registers.................................................... 92
Timer1
Timer2
A/D Conversion ......................................................... 253
A/D Conversion (Sleep Mode) .................................. 254
Asynchronous Reception .......................................... 156
Asynchronous Transmission ..................................... 152
Asynchronous Transmission (Back to Back) ............ 152
Auto Wake-up Bit (WUE) During Normal Operation . 166
Auto Wake-up Bit (WUE) During Sleep .................... 167
Automatic Baud Rate Calculator ............................... 165
Brown-out Reset (BOR) ............................................ 241
Brown-out Reset Situations ...................................... 198
CLKOUT and I/O....................................................... 240
Clock Synchronization .............................................. 192
Clock Timing ............................................................. 238
Comparator Output ..................................................... 93
Enhanced Capture/Compare/PWM (ECCP) ............. 244
EUSART Synchronous Receive (Master/Slave) ....... 246
EUSART Synchronous Transmission
Fail-Safe Clock Monitor (FSCM) ................................. 58
Full-Bridge PWM Output ........................................... 138
Half-Bridge PWM Output .................................. 136, 143
I
I
I
I
I
I
INT Pin Interrupt........................................................ 206
Internal Oscillator Switch Timing................................. 54
PWM Auto-shutdown
PWM Direction Change ............................................ 139
PWM Direction Change at Near 100% Duty Cycle ... 140
PWM Output (Active-High)........................................ 134
PWM Output (Active-Low) ........................................ 135
Reset, WDT, OST and Power-up Timer ................... 241
Send Break Character Sequence ............................. 168
Slave Synchronization .............................................. 181
SPI Master Mode (CKE = 1, SMP = 1) ..................... 247
SPI Mode (Master Mode) .......................................... 180
SPI Mode (Slave Mode with CKE = 0) ...................... 182
SPI Mode (Slave Mode with CKE = 1) ...................... 182
SPI Slave Mode (CKE = 0) ....................................... 248
SPI Slave Mode (CKE = 1) ....................................... 248
Synchronous Reception (Master Mode, SREN) ....... 172
Synchronous Transmission....................................... 170
Synchronous Transmission (Through TXEN) ........... 170
Time-out Sequence
Timer0 and Timer1 External Clock ........................... 243
Timer1 Incrementing Edge.......................................... 87
Two Speed Start-up .................................................... 56
Wake-up from Interrupt ............................................. 211
2
2
2
2
2
2
C Bus Data ............................................................. 250
C Bus Start/Stop Bits.............................................. 249
C Reception (7-bit Address) ................................... 186
C Slave Mode (Transmission, 10-bit Address) ....... 190
C Slave Mode with SEN = 0 (Reception,
C Transmission (7-bit Address) .............................. 189
T1CON................................................................ 88
T2CON................................................................ 92
(Master/Slave)................................................... 246
10-bit Address).................................................. 188
Auto-restart Enabled ......................................... 142
Firmware Restart .............................................. 142
Case 1............................................................... 200
Case 2............................................................... 200
Case 3............................................................... 200
Timing Parameter Symbology .......................................... 237
Timing Requirements
TRISA
TRISA Register................................................................... 59
TRISB
TRISB Register................................................................... 70
TRISC
TRISC Register................................................................... 76
Two-Speed Clock Start-up Mode........................................ 55
TXREG ............................................................................. 151
TXSTA Register................................................................ 158
U
UA..................................................................................... 176
Ultra Low-Power Wake-up.............. 14, 16, 18, 20, 22, 60, 63
Update Address bit, UA .................................................... 176
V
Voltage Reference (VR)
Voltage Reference. See Comparator
Voltage References
VRCON Register .............................................................. 106
V
W
Wake-up on Break ............................................................ 166
Wake-up Using Interrupts ................................................. 210
Watchdog Timer (WDT).................................................... 208
WCOL bit .......................................................................... 177
WDTCON Register ........................................................... 209
WPUA Register................................................................... 62
WPUB Register................................................................... 70
Write Collision Detect bit (WCOL) .................................... 177
WWW Address ................................................................. 289
WWW, On-Line Support ....................................................... 8
REF
I
I2C Bus Start/Stop Bits ............................................. 250
SPI Mode .................................................................. 249
Registers .................................................................... 59
Registers .................................................................... 69
Registers .................................................................... 76
BRGH Bit .................................................................. 161
Specifications ........................................................... 245
Voltage Reference (CV
Associated registers ................................................. 106
VP6 Stabilization ...................................................... 105
Associated registers ................................................. 209
Clock Source ............................................................ 208
Modes ....................................................................... 208
Period ....................................................................... 208
Specifications ........................................................... 242
. S
2
C Bus Data............................................................. 251
EE
ADC Reference Voltage
© 2007 Microchip Technology Inc.
REF
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