PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 170
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PIC18F4431-I/P
Manufacturer Part Number
PIC18F4431-I/P
Description
Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4431-IP.pdf
(396 pages)
Specifications of PIC18F4431-I/P
A/d Inputs
9-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18F2331/2431/4331/4431
FIGURE 16-7:
16.1.8
The
(CAP1M3:CAP1M0 = 1110 or 1111) enables the
Special Event Trigger signal. The trigger signal can be
used as the Special Event Reset input to TMR5,
resetting the timer when the specific event happens on
IC1. The events are summarized in Table 16-2.
TABLE 16-2:
16.1.9
Table 16-3 shows a summary of the input capture con-
figuration when used in conjunction with TMR5 timer
resource.
DS39616B-page 168
TMR5 Reset
TMR5ON
Note 1: Timer5 is only reset and enabled (assuming: TMR5ON = 0 and TMR5MOD = 1) when the Special Event Reset Trigger
CAP1M3:
CAP1M0
CAP1 pin
1110
1111
TMR5
Special
IC1IF
OSC
(1)
is enabled for the Timer5 Reset input. TMR5ON bit is asserted and Timer5 is reset on the Q1 rising edge following the
event capture. With the Special Event Reset Trigger disabled, Timer5 cannot be reset by the Special Event Reset
Trigger on CAP1 input. In order for the Special Event Reset Trigger to work as the Reset trigger to Timer5, IC1 must be
configured in the Special Event Trigger mode (CAP1M<3:0> = 1110 or 1111).
SPECIAL EVENT TRIGGER (CAP1
ONLY)
OPERATING MODES SUMMARY
Q1
The trigger occurs on every falling
edge on CAP1 input
The trigger occurs on every rising
edge on CAP1 input
Event
SPECIAL EVENT TRIGGER
Q2
XXXX
CAPXIF INTERRUPTS AND IC1 SPECIAL EVENT TRIGGER
Q3
Trigger
Description
Q4
Q1
mode
Q2
of
Q3
Preliminary
IC1
Q4
Q1
Q2
16.1.10
Although the IC and QEI submodules are mutually
exclusive, the IC can be reconfigured to work with the
QEI module to perform specific functions. In effect, the
QEI “borrows” hardware from the IC to perform these
operations.
For velocity measurement, the QEI uses dedicated
hardware in channel IC1. The CAP1BUF registers are
remapped, becoming the VREG registers. Its operation
and use are described in Section 16.2.6 “Velocity
Measurement”.
While in QEI mode, the CAP2BUF and CAP3BUF reg-
isters of channel IC2 and IC3 are used for position
determination. They are remapped as the POSCNT
and MAXCNT buffer registers, respectively.
Q3
Q4
OTHER OPERATING MODES
Q1
Q2
0000
Q3
2003 Microchip Technology Inc.
Q4
Q1
Q2
0001
Q3
Q4
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