PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 48

• Manufacturer Part Number: PIC18F4431-I/P
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4431-I/P

• A/d Inputs: 9-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2331/2431/4331/4431
4.1
A Power-on Reset pulse is generated on-chip when
V
cuitry, just tie the MCLR pin through a resistor (1k to
10 k ) to V
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for V
(parameter D004). For a slow rise time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
FIGURE 4-2:
4.2
The Power-up Timer (PWRT) of the PIC18F2331/2431/
4331/4431 devices is an 11-bit counter, which uses the
INTRC source as the clock input. This yields a count of
2048 x 32 s = 65.6 ms. While the PWRT is counting,
the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter #33 for details.
The PWRT is enabled by clearing configuration bit
PWRTEN.
DS39616B-page 46
DD
Note 1: External Power-on Reset circuit is
rise is detected. To take advantage of the POR cir-
V
2: R < 40 k
3: R1
Power-on Reset (POR)
Power-up Timer (PWRT)
DD
DD
D
required only if the V
is too slow. The diode D helps discharge
the capacitor quickly when V
down.
sure that the voltage drop across R does
not violate the device’s electrical specifi-
cation.
into MCLR from external capacitor C, in
the event of MCLR/V
due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
. This will eliminate external RC compo-
V
DD
1 k
R
C
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
will limit any current flowing
is recommended to make
R1
DD
DD
PIC18FXXXX
PP
MCLR
POWER-UP)
power-up slope
pin breakdown,
DD
DD
is specified
powers
Preliminary
4.3
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes, and only on Power-on Reset or on exit
from most power-managed modes.
4.4
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A portion of the Power-
up Timer is used to provide a fixed time-out that is suf-
ficient for the PLL to lock to the main oscillator fre-
quency. This PLL lock time-out (T
and follows the oscillator start-up time-out.
4.5
A configuration bit, BOREN, can disable (if clear/
programmed) or enable (if set) the Brown-out Reset cir-
cuitry. If V
greater than T
ation will reset the chip. A Reset may not occur if V
falls below V
remain in Brown-out Reset until V
If the Power-up Timer is enabled, it will be invoked after
V
Reset for an additional time delay T
#33). If V
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
V
the additional time delay. Enabling BOR Reset does
not automatically enable the PWRT.
4.6
On power-up, the time-out sequence is as follows:
First, after the POR pulse has cleared, PWRT time-out
is invoked (if enabled). Then, the OST is activated. The
total time-out will vary based on oscillator configuration
and the status of the PWRT. For example, in RC mode
with the PWRT disabled, there will be no time-out at all.
Figures 4-3 through 4-7 depict time-out sequences on
power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bring-
ing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
Table 4-2 shows the Reset conditions for some Special
Function registers, while Table 4-3 shows the Reset
conditions for all the registers.
DD
DD
rises above V
rises above V
Oscillator Start-up Timer (OST)
PLL Lock Time-out
Brown-out Reset (BOR)
Time-out Sequence
DD
DD
BOR
drops below V
BOR
falls below V
BOR
(parameter #35), the brown-out situ-
for less than T
BOR
, the Power-up Timer will execute
; it then will keep the chip in
 2003 Microchip Technology Inc.
BOR
BOR
(parameter D005) for
DD
PLL
while the Power-up
BOR
rises above V
PWRT
) is typically 2 ms
. The chip will
(parameter
BOR
DD
.