PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 212
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F4431-I/P
Manufacturer Part Number
PIC18F4431-I/P
Description
Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4431-IP.pdf
(396 pages)
Specifications of PIC18F4431-I/P
A/d Inputs
9-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18F2331/2431/4331/4431
TABLE 17-6:
DS39616B-page 210
INTCON
IPR3
PIE3
PIR3
PTCON0
PTCON1
PTMRL
PTMRH
PTPERL
PTPERH
SEVTCMPL
SEVTCMPH
PWMCON0
PWMCON1
DTCON
FLTCONFIG
OVDCOND
OVDCONS
PDC0L
PDC0H
PDC1L
PDC1H
PDC2L
PDC2H
PDC3L
PDC3H
Legend:
Note
Name
(1)
(1)
(1)
(1,2)
(1)
(1)
(1)
(1)
(1,2)
1:
2:
(1)
(1)
(1)
(1)
(1)
- = Unimplemented, u = Unchanged. Shaded cells are not used with the power control PWM.
Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to.
Unimplemented in PIC18F2X31 devices; maintain these bits clear. Reset values shown are for PIC18F4X31 devices.
GIE/GIEH PEIE/GIEL
PWM Time Base (lower 8 bits)
PWM Time Base Period (lower 8 bits)
PWM Special Event Compare (lower 8 bits)
SEVOPS3 SEVOPS2
PWM Duty Cycle #0L register (lower 8 bits)
PWM Duty Cycle #1L register (lower 8 bits)
PWM Duty Cycle #2L register (Lower 8 bits)
PWM Duty Cycle #3L register (Lower 8 bits)
POVD7
POUT7
PTOPS3
BRFEN
DTPS1
PTEN
Bit 7
—
—
—
—
—
—
—
—
—
—
—
REGISTERS ASSOCIATED WITH THE POWER CONTROL PWM MODULE
(2)
(2)
PWMEN2
POVD6
POUT6
FLTBS
PTOPS2
DTPS0
PTDIR
Bit 6
—
—
—
—
—
—
—
—
—
—
(2)
(2)
(2)
Dead Time A Value register
PWM Duty Cycle #0H register (upper 6 bits)
PWM Duty Cycle #1H register (upper 6 bits)
PWM Duty Cycle #2H register (Upper 6 bits)
PWM Duty Cycle #3H register (Upper 6 bits)
FLTBMOD
SEVOPS1
PWMEN1
PTOPS1
TMR0IE
POVD5
POUT5
Bit 5
—
—
—
—
—
—
—
(2)
FLTBEN
SEVOPS0 SEVTDIR
PWMEN0 PMOD3
PTOPS0
POVD4
POUT4
INT0IE
Bit 4
PTIP
PTIE
PTIF
—
—
—
—
Preliminary
(2)
PWM Time Base (upper 4 bits)
PWM Time Base Period (upper 4 bits)
PWM Special Event Compare (upper 4 bits)
PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 0000 0000 0000 0000
IC3DRIP
IC3DRIE
IC3DRIF
FLTCON
POVD3
POUT3
RBIE
Bit 3
—
(2)
IC2QEIP
IC2QEIE
IC2QEIF
TMR0IF
PMOD2
POVD2
POUT2
FLTAS
Bit 2
—
—
FLTAMOD FLTAEN
PMOD1
POVD1
POUT1
INT0IF
IC1IP
IC1IE
IC1IF
UDIS
Bit 1
—
TMR5IP
TMR5IE
TMR5IF
2003 Microchip Technology Inc.
PMOD0
OSYNC
POVD0
POUT0
RBIF
Bit 0
—
0000 000x 0000 000u
---1 1111 ---1 1111
---0 0000 ---0 0000
---0 0000 ---0 0000
00-- ---- 00-- ----
0000 0000 0000 0000
---- 0000 ---- 0000
1111 1111 1111 1111
---- 1111 ---- 1111
0000 0000 0000 0000
---- 0000 ---- 0000
-101 0000 -101 0000
0000 0-00 0000 0-00
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
--00 0000 --00 0000
0000 0000 0000 0000
0000 0000 0000 0000
--00 0000 --00 0000
0000 0000 0000 0000
--00 0000 --00 0000
0000 0000 0000 0000
--00 0000 --00 0000
Value on:
POR,
BOR
Value on
all other
Resets
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