PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 91

• Manufacturer Part Number: PIC18F4431-I/P
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4431-I/P

• A/d Inputs: 9-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

8.0
8.1
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F2331/2431/4331/4431 devices. By making
the multiply a hardware operation, it completes in a
single instruction cycle. This is an unsigned multiply
that gives a 16-bit result. The result is stored into the
16-bit product register pair (PRODH:PRODL). The
multiplier does not affect any flags in the Status
register.
TABLE 8-1:
8.2
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
 2003 Microchip Technology Inc.
16 x 16 unsigned
8 x 8 unsigned
16 x 16 signed
8 x 8 signed
Routine
8 X 8 HARDWARE MULTIPLIER
Introduction
Operation
PERFORMANCE COMPARISON
Without hardware multiply
Without hardware multiply
Without hardware multiply
Without hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Multiply Method
PIC18F2331/2431/4331/4431
Preliminary
Program
Memory
(Words)
13
33
21
24
52
36
1
6
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
EXAMPLE 8-1:
EXAMPLE 8-2:
MOVF
MULWF
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
algorithms
Cycles
(Max)
242
254
69
91
24
36
1
6
ARG1, W
ARG2
ARG1,
ARG2
ARG2,
PRODH, F
ARG2,
ARG1,
PRODH, F
@ 40 MHz
24.2 s
25.4 s
100 ns
600 ns
6.9 s
9.1 s
2.4 s
3.6 s
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8 x 8 SIGNED MULTIPLY
ROUTINE
W
SB
W
SB
;
; ARG1 * ARG2 ->
; PRODH:PRODL
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
; Test Sign Bit
; PRODH = PRODH
;
@ 10 MHz
102.6 s
27.6 s
36.4 s
96.8 s
14.4 s
Time
400 ns
2.4 s
9.6 s
DS39616B-page 89
- ARG1
- ARG2
@ 4 MHz
242 s
254 s
69 s
91 s
24 s
36 s
1 s
6 s