PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 179

• Manufacturer Part Number: PIC18F4431-I/P
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4431-I/P

• A/d Inputs: 9-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 16-13:
16.2.6.2
The velocity event pulse (velcap, see Figure 16-12)
serves as the TMR5 capture trigger to IC1 while in the
Velocity mode. The number of velocity events are
reduced by the velocity postscaler before they are used
as the input capture clock. The velocity event reduction
ratio can be set with the PDEC1:PDEC0 control bits
(QEICON<1:0>) to 1:4, 1:16, 1:64 or no reduction (1:1).
The velocity postscaler settings are automatically
reloaded from their previous values as the Velocity
mode is re-enabled.
 2003 Microchip Technology Inc.
Note 1: Timing shown is for QEIM<2:0> = 101, 110 or 111 (x4 Update mode enabled) and the velocity postscaler divide ratio
Instr.
Execution
2: VELR register latches the TMR5 count on the “velcap” capture pulse. Timer5 must be set to the synchronous timer or
3: The TMR5 counter is reset on the next Q1 clock cycle following the “velcap” pulse. TMR5 value is unaffected when the
4: IC1IF interrupt is enabled by setting IC1IE as follows, BSF PIE2, IC1IE. Assume IC1E bit is placed in PIE2 Peripheral
5: Post decimation value is changed from PDEC = 01 (decimate by 4) to PDEC = 00 (decimate by 1).
is set to divide by 4 (PDEC<1:0> = 01).
Counter mode. In this example, it is set to the Synchronous Timer mode where the TMR5 prescaler divide ratio = 1
(i.e., Timer5 clock = T
Velocity Measurement mode is first enabled (VELM = 0). The velocity postscaler values must be reconfigured to their
previous settings when re-entering Velocity Measurement mode. While making speed measurements of very slow
rotational speeds (e.g., servo-controller applications), the Velocity Measurement mode may not provide sufficient
precision. The Pulse Width Measurement mode may have to be used to provide the additional precision. In this case,
the input pulse is measured on the CAP1 input pin.
Interrupt Enable register in the target device. The actual IC1IF bit is written on Q2 rising edge.
QEA
QEB
vel_out
velcap
TMR5
VELR
cnt_reset
IC1IF
CAP1REN
Velocity Postscaler
BCF TMR5CON, VELM
(4)
(2)
(2)
(3)
VELOCITY MEASUREMENT TIMING
CY
).
BCF PIE2, IC1IE
Old Value
PIC18F2331/2431/4331/4431
Q1
BSF PIE2, IC1IE
Preliminary
1529
Forward
16.2.6.3
The TMR5 value can be reset (TMR5 register pair =
0000h) on a velocity event capture by setting the
CAP1REN bit (CAP1CON<6>). When CAP1REN is
cleared, the TMR5 time base will not be reset on any
velocity event capture pulse. The VELR register pair,
however, will continue to be updated with the current
TMR5 value.
Q1
(1)
MOVWF QEICON
1537
CAP1REN in Velocity Mode
Reverse
(5)
Q1
DS39616B-page 177