PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 227

• Manufacturer Part Number: PIC18F4431-I/P
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4431-I/P

• A/d Inputs: 9-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

19.2
The BRG is a dedicated 8-bit or 16-bit generator, that
supports both the Asynchronous and Synchronous
modes of the USART. By default, the BRG operates in
8-bit mode; setting the BRG16 bit (BAUDCTL<3>)
selects 16-bit mode.
The SPBRGH:SPBRG register pair controls the period
of a free running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 also control the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 19-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internally generated clock).
Given the desired baud rate and F
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 19-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 19-1. Typical baud
rates and error values for the various asynchronous
modes are shown in Table 19-2. It may be advanta-
geous to use the high baud rate (BRGH = 1), or the 16-
bit BRG to reduce the baud rate error, or achieve a slow
baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
TABLE 19-1:
 2003 Microchip Technology Inc.
Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair
SYNC
0
0
0
0
1
1
USART Baud Rate Generator
(BRG)
Configuration Bits
BAUD RATE FORMULAS
BRG16
0
0
1
1
0
1
BRGH
0
1
0
1
x
x
OSC
, the nearest
PIC18F2331/2431/4331/4431
Preliminary
16-bit/Asynchronous
16-bit/Asynchronous
BRG/USART Mode
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Synchronous
8-bit/Synchronous
19.2.1
The system clock is used to generate the desired baud
rate; however, when a power-managed mode is
entered, the clock source may be operating at a
different frequency than in PRI_RUN mode. In Sleep
mode, no clocks are present and in PRI_IDLE, the
primary clock source continues to provide clocks to the
baud rate generator; however, in other power-
managed modes, the clock frequency will probably
change. This may require the value in SPBRG to be
adjusted.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit
and make sure that the receive operation is Idle before
changing the system clock.
19.2.2
The data on the RC7/RX/DT/SDO pin is sampled three
times by a majority detect circuit to determine if a high
or a low level is present at the RX pin.
POWER-MANAGED MODE
OPERATION
SAMPLING
Baud Rate Formula
F
F
F
OSC
OSC
OSC
/[64 (n+1)]
/[16 (n+1)]
/[4 (n+1)]
DS39616B-page 225