PIC16F72-I/SP Microchip Technology Inc., PIC16F72-I/SP Datasheet - Page 27

• Manufacturer Part Number: PIC16F72-I/SP
• Description: 28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F72-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.3
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
EXAMPLE 3-3:
 2002 Microchip Technology Inc.
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
PORTC and the TRISC Register
PORTC
PORTC
TRISC
0xCF
TRISC
INITIALIZING PORTC
; Select Bank for PORTC
; Initialize PORTC by
; clearing output
; data latches
; Select Bank for TRISC
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
FIGURE 3-5:
Peripheral
OE
Note 1: Port/Peripheral select signal selects
Peripheral Input
WR
TRIS
Peripheral Data Out
Data
Bus
WR
Port
Port/Peripheral Select
(2)
2: Peripheral OE (output enable) is only
RD
Port
between port data and peripheral output.
activated if peripheral select is active.
TRIS Latch
Data Latch
D
D
CK
RD TRIS
CK
Q
Q
Q
Q
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
(1)
0
1
Q
PIC16F72
EN
D
Schmitt
Trigger
DS39597B-page 25
V
V
N
P
SS
DD
V
V
DD
SS
I/O
pin