PIC16F72-I/SP Microchip Technology Inc., PIC16F72-I/SP Datasheet - Page 37

• Manufacturer Part Number: PIC16F72-I/SP
• Description: 28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F72-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.0
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to
Timer2 has a control register, shown in Register 7-1.
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 7-1 is a simplified block diagram of the Timer2
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Reference Manual,
(DS33023).
7.1
Timer2 can be used as the PWM time-base for PWM
mode of the CCP module.
The TMR2 register is readable and writable, and is
cleared on any device RESET.
The input clock (F
1:4
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
 2002 Microchip Technology Inc.
generate clock shift
or
TIMER2 MODULE
Timer2 Operation
1:16,
OSC
selected
/4) has a prescale option of 1:1,
by
control
bits
7.2
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device RESET (Power-on Reset, MCLR ,
TMR2 is not cleared when T2CON is written.
7.3
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
7.4
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module, which optionally uses
it to generate a shift clock.
FIGURE 7-1:
Note 1: TMR2 register output can be software
WDT Reset, or Brown-out Reset)
Sets Flag
bit TMR2IF
1:1
Postscaler
Timer2 Prescaler and Postscaler
Timer2 Interrupt
Output of TMR2
to
selected by the SSP module as a baud clock.
1:16
4
TMR2
Output
RESET
EQ
(1)
Comparator
TIMER2 BLOCK DIAGRAM
TMR2 reg
PR2 reg
PIC16F72
1:1, 1:4, 1:16
Prescaler
DS39597B-page 35
2
F
OSC
/4