PIC16F72-I/SP Microchip Technology Inc., PIC16F72-I/SP Datasheet - Page 97

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PIC16F72-I/SP

Manufacturer Part Number
PIC16F72-I/SP
Description
28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC16F72-I/SP

A/d Inputs
5-Channel, 8-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
22
Interface
I2C/SPI
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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FIGURE 14-5:
TABLE 14-2:
 2002 Microchip Technology Inc.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x T
Param
22††*
23††*
No.
10*
11*
12*
13*
14*
15*
16*
17*
18*
19*
20*
21*
(Output)
Note: Refer to Figure 14-3 for load conditions.
I/O Pin
I/O Pin
(Input)
OSC1
CLKO
*
†† These parameters are asynchronous events, not related to any internal clock edges.
TosH2ckL
TosH2ckH OSC1 ↑ to CLKO ↑
TckR
TckF
TckL2ioV
TioV2ckH
TckH2ioI
TosH2ioV
TosH2ioI
TioV2osH
TioR
TioF
T
T
INP
RBP
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Symbol
CLKO AND I/O TIMING REQUIREMENTS
OSC1 ↑ to CLKO ↓
CLKO rise time
CLKO fall time
CLKO ↓ to Port out valid
Port in valid before CLKO ↑
Port in hold after CLKO ↑
OSC1 ↑ (Q1 cycle) to Port out valid
OSC1 ↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
Port input valid to OSC1 ↑ (I/O in setup time)
Port output rise time
Port output fall time
INT pin high or low time
RB7:RB4 change INT high or low time
Old Value
CLKO AND I/O TIMING
Q4
Characteristic
10
13
Standard (F)
Extended (LF)
Standard (F)
Extended (LF)
Standard (F)
Extended (LF)
17
14
20, 21
Q1
19
18
T
OSC
OSC
Min
100
200
T
T
0
0
CY
CY
+ 200
.
Q2
15
Typ†
100
75
75
35
35
10
10
0.5 T
Max
200
200
100
100
255
145
145
11
CY
40
40
12
PIC16F72
+ 20
New Value
16
DS39597B-page 95
Q3
Units Conditions
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)

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