PIC16F72-I/SP Microchip Technology Inc., PIC16F72-I/SP Datasheet - Page 59

• Manufacturer Part Number: PIC16F72-I/SP
• Description: 28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F72-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

10.5
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared,
and the result loaded into the ADRES register. If the
A/D interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
TABLE 10-2:
 2002 Microchip Technology Inc.
0Bh,8Bh
10Bh,18Bh
0Ch
8Ch
1Eh
1Fh
9Fh
05h
85h
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Address
Note:
A/D Operation During SLEEP
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction
instruction that sets the GO/DONE bit.
INTCON
PIR1
PIE1
ADRES
ADCON0 ADCS1 ADCS0
ADCON1
PORTA
TRISA
Name
REGISTERS/BITS ASSOCIATED WITH A/D
A/D Result Register
Bit 7
GIE
—
—
—
—
—
immediately
ADIE
Bit 6
PEIE
ADIF
—
—
—
PORTA Data Direction Register
TMR0IE INTE
CHS2
follows
Bit 5
RA5
—
—
—
CHS1 CHS0 GO/DONE
Bit 4
RA4
—
—
—
the
SSPIF
SSPIE
RBIE
Bit 3
RA3
—
10.6
A device RESET forces all registers to their RESET
state. The A/D module is disabled and any conversion
in progress is aborted. All A/D input pins are configured
as analog inputs.
The ADRES register will contain unknown data after a
Power-on Reset.
10.7
An A/D conversion can be started by the “special event
trigger” of the CCP1 module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
grammed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRES to
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
done before the “special event trigger” sets the
GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
TMR0IF
CCP1IF
CCP1IE
PCFG2
Bit 2
RA2
Effects of a RESET
Use of the CCP Trigger
TMR2IF TMR1IF -0-- 0000
TMR2IE TMR1IE -0-- 0000
PCFG1
INTF
Bit 1
RA1
—
PCFG0
ADON
RBIF
Bit 0
RA0
0000 000x
xxxx xxxx
0000 00-0
---- -000
--0x 0000
--11 1111
POR, BOR
PIC16F72
Value on
DS39597B-page 57
0000 000u
-0-- 0000
-0-- 0000
uuuu uuuu
0000 00-0
---- -000
--0u 0000
--11 1111
Value on
all other
RESETS