PIC16F72-I/SP Microchip Technology Inc., PIC16F72-I/SP Datasheet - Page 46

• Manufacturer Part Number: PIC16F72-I/SP
• Description: 28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F72-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F72
REGISTER 9-1:
DS39597B-page 44
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h)
bit 7
SMP: SPI Data Input Sample Phase bits
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time (Microwire
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
I
This bit must be maintained clear
CKE: SPI Clock Edge Select bits (Figure 9-2, Figure 9-3, and Figure 9-4)
SPI mode, CKP = 0:
1 = Data transmitted on rising edge of SCK (Microwire alternate)
0 = Data transmitted on falling edge of SCK
SPI mode, CKP = 1:
1 = Data transmitted on falling edge of SCK (Microwire default)
0 = Data transmitted on rising edge of SCK
I
This bit must be maintained clear
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: STOP bit (I
the START bit is detected last. SSPEN is cleared.
1 = Indicates that a STOP bit has been detected last (this bit is ‘0’ on RESET)
0 = STOP bit was not detected last
S: START bit (I
the STOP bit is detected last. SSPEN is cleared.
1 = Indicates that a START bit has been detected last (this bit is ‘0’ on RESET)
0 = START bit was not detected last
R/W: Read/Write Information bit (I
ing the last address match. This bit is only valid from the address match to the next START bit,
STOP bit, or ACK bit.
1 = Read
0 = Write
UA: Update Address bit (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
Legend:
R = Readable bit
- n = Value at POR
2
2
C mode:
C mode:
R/W-0
SMP
2
C mode only):
R/W-0
2
CKE
C mode only) – This bit is cleared when the SSP module is disabled, or when
2
C mode only) – This bit is cleared when the SSP module is disabled, or when
2
C modes):
2
C mode only)
R-0
D/A
W = Writable bit
‘1’ = Bit is set
2
C mode only)
2
C mode only) – This bit holds the R/W bit information follow-
R-0
P
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0
S
R/W
®
R-0
 2002 Microchip Technology Inc.
)
x = Bit is unknown
R-0
UA
R-0
BF
bit 0