ICS1893CY-10LF IDT, Integrated Device Technology Inc, ICS1893CY-10LF Datasheet - Page 107

• Manufacturer Part Number: ICS1893CY-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893CY-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1893CY-10LF; 800-1025

8.3.4.1 MAC/Repeater Interface Pins for Media Independent Interface
ICS1893CY-10 Rev 1/07
Table 8-5
Table 8-5. MAC/Repeater Interface Pins: Media Independent Interface (MII)
COL
CRS
MDC
MDIO
Name
Pin
ICS1893CY-10 - Release
lists the MAC/Repeater Interface pin descriptions for the MII.
Number
Pin
49
50
31
30
Output
Output
Output
Input/
Type
Input
Pin
Copyright © 2007, Integrated Device Technology, Inc.
Collision (Detect).
The ICS1893CY-10 asserts a signal on the COL pin when the
ICS1893CY-10 detects receive activity while transmitting (that is, while the
TXEN signal is asserted by the MAC/repeater, that is, when transmitting).
When the mode is:
Carrier Sense.
When the ICS1893CY-10 mode is:
Management Data Clock.
The ICS1893CY-10 uses the signal on the MDC pin to synchronize the
transfer of management information between the ICS1893CY-10 and the
Station Management Entity (STA), using the serial MDIO data line. The
MDC signal is sourced by the STA.
Management Data Input/Output.
The signal on this pin can be tri-stated and can be driven by one of the
following:
All transfers and sampling are synchronous with the signal on the MDC
pin.
Note:
Note: If the ICS1893CY-10 is to be used in an application that uses the
1. The signal on the COL pin is not synchronous to either RXCLK or
2. In full-duplex mode, the COL signal is disabled and always remains
3. The COL signal is asserted as part of the signal quality error (SQE)
•
•
•
•
Note: The signal on the CRS pin is not synchronous to the signal on
•
•
10Base-T, the ICS1893CY-10 detects receive activity by monitoring
the un-squelched MDI receive signal.
100Base-TX, the ICS1893CY-10 detects receive activity when there
are two non-contiguous zeros in any 10-bit symbol derived from the
MDI receive data stream.
Half-duplex, the ICS1893CY-10 asserts a signal on its CRS pin when it
detects either receive or transmit activity.
Either full-duplex or Repeater mode, the ICS1893CY-10 asserts a
signal on its CRS pin only in response to receive activity.
A Station Management Entity (STA), to transfer command and data
information to the registers of the ICS1893CY-10.
The ICS1893CY-10, to transfer status information.
TXCLK.
low.
test. This assertion can be suppressed with the SQE Test Inhibit bit (bit
18.2).
mechanical MII specification, MDIO must have a 1.5 k Ω ±5%
pull-up resistor at the ICS1893CY-10 end and a 2 k Ω ±5%
pull-down resistor at the station management end. (These resistors
enable the station management to determine if the connection is
intact.)
either the RXCLK or TXCLK pin.
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107
Chapter 8 Pin Diagram, Listings, and Descriptions
Pin Description