ICS1893CY-10LF IDT, Integrated Device Technology Inc, ICS1893CY-10LF Datasheet - Page 51

• Manufacturer Part Number: ICS1893CY-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893CY-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1893CY-10LF; 800-1025

6.5.8 10Base-T Operation: Collision Detection
6.5.9 10Base-T Operation: Jabber
6.5.10 10Base-T Operation: SQE Test
ICS1893CY-10 Rev 1/07
The ICS1893CY-10 has a 10Base-T Collision Detection Function that establishes the state of its Collision
Detection signal (COL) based upon both (1) the state of its Receiver state machine and (2) the state of its
Transmit state machine. When the ICS1893CY-10 is operating in:
•
•
The ICS1893CY-10 has an ISO/IEC compliant Jabber Detection Function that, when enabled, monitors the
data stream sent to its Twisted-Pair Transmitter to ensure that it does not exceed the 10Base-T Jabber
activation time limit (that is, the maximum transmission time). For more information, see
“10Base-T: Jabber
When the Jabber Detection Function detects that its transmission time exceeds the maximum Jabber
activation time limit and Jabber Detection is enabled, the ICS1893CY-10 asserts its Collision Detect (COL)
signal. During this ISO/IEC specified ‘jabber de-activation time’, the ICS1893CY-10 transmit data stream is
interrupted and prevented from reaching its Twisted-Pair Transmitter. During this time, when interrupting
the data stream and asserting its COL signal, the ICS1893CY-10 transmits Normal Link Pulses and sets its
QuickPoll Detailed Status Register’s Jabber Detected bit (bit 17.2) to logic one. This bit is a latching high
(LH) bit. (For more information on latching high and latching low bits, see
Bits”
The ICS1893CY-10 provides an STA with the ability to disable the Jabber Detection Function using the
Jabber Inhibit bit (bit 18.5 in the 10Base-T Operations Register). Setting bit 18.5 to logic:
•
•
The ICS1893CY-10 has an ISO/IEC compliant Signal Quality Error (SQE) Test Function used exclusively
for 10Base-T operations. When enabled, the ICS1893CY-10 performs the SQE Test at the completion of
each transmitted packet (that is, whenever its TX_EN signal transitions from asserted to de-asserted).
When the ICS1893CY-10 executes its SQE Test, it asserts the COL signal to its MAC Interface for a
pre-determined time duration (ISO/IEC specified). [For more information, see
Heartbeat Timing
An ICS1893CY-10 SQE Test Function is:
•
•
Half-duplex mode, the ICS1893CY-10 asserts its COL signal to indicate it is receiving data while
transmission of data is also in progress.
Full-duplex mode, the ICS1893CY-10 always sets its COL signal to FALSE.
Zero (the default) enables the Jabber Detection Function.
One disables the Jabber Detection Function.
Enabled only when all the following conditions are true:
Disabled whenever any of the following are true:
– The ICS1893CY-10 is in node mode.
– The ICS1893CY-10 is in half-duplex mode.
– The ICS1893CY-10 has a valid link.
– The 10Base-T Operations Register’s SQE Test Inhibit bit (bit 18.2) is logic zero (the default).
– The ICS1893CY-10 TX_EN signal has transitioned from asserted (high) to de-asserted (low).
– The ICS1893CY-10 is in Repeater mode.
– The ICS1893CY-10 is in full-duplex mode.
– The ICS1893CY-10 detects a link failure.
ICS1893CY-10 - Release
and
Section 7.1.4.2, “Latching Low
(SQE)”.]
Timing”.
Copyright © 2007, Integrated Device Technology, Inc.
Bits”.)
All rights reserved.
51
Section 7.1.4.1, “Latching High
Section 9.5.19, “10Base-T:
Chapter 6 Functional Blocks
Section 9.5.20,