ICS1893CY-10LF IDT, Integrated Device Technology Inc, ICS1893CY-10LF Datasheet - Page 17

• Manufacturer Part Number: ICS1893CY-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893CY-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1893CY-10LF; 800-1025

4.1 Reset Operations
4.1.1 General Reset Operations
4.1.1.1 Entering Reset
4.1.1.2 Exiting Reset
4.1.1.3 Hot Insertion
ICS1893CY-10 Rev 1/07
This section first discusses reset operations in general and then specific ways in which the ICS1893CY-10
can be configured for various reset options.
The following reset operations apply to all the specific ways in which the ICS1893CY-10 can be reset,
which are discussed in
When the ICS1893CY-10 enters a reset condition (either through hardware, power-on reset, or software), it
does the following:
1. Isolates the MAC/Repeater Interface input pins
2. Drives all MAC/Repeater Interface output pins low
3. Tri-states the signals on its Twisted-Pair Transmit pins (TP_TXP and TP_TXN)
4. Initializes all its internal modules and state machines to their default states
5. Enters the power-down state
6. Initializes all internal latching low (LL), latching high (LH), and latching maximum (LMX) Management
When the ICS1893CY-10 exits a reset condition, it does the following:
1. Exits the power-down state
2. Latches the Serial Management Port Address of the ICS1893CY-10 into the Extended Control
3. Enables all its internal modules and state machines
4. Sets all Management Register bits to either (1) their default values or (2) the values specified by their
5. Enables the Twisted-Pair Transmit pins (TP_TXP and TP_TXN)
6. Resynchronizes both its Transmit and Receive Phase-Locked Loops, which provide its transmit clock
7. Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition
As with the ICS189X products, the ICS1893CY-10 reset design supports ‘hot insertion’ of its MII. (That is,
the ICS1893CY-10 can connect its MAC/Repeater Interface to a MAC/repeater while power is already
applied to the MAC/repeater.)
ICS1893CY-10 - Release
Register bits to their default values
Register, bits 16.10:6. [See
associated ICS1893CY-10 input pins, as determined by the HW/SW pin
(TXCLK) and receive clock (RXCLK)
is removed
Section 4.1.2, “Specific Reset
Copyright © 2007, Integrated Device Technology, Inc.
Section 7.11.3, “PHY Address (bits
All rights reserved.
17
Operations”.
16.10:6)”.]
Chapter 4 Operating Modes Overview