ICS1893CY-10LF IDT, Integrated Device Technology Inc, ICS1893CY-10LF Datasheet - Page 68

• Manufacturer Part Number: ICS1893CY-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893CY-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1893CY-10LF; 800-1025

7.3.12 Jabber Detect (bit 1.1)
7.3.13 Extended Capability (bit 1.0)
ICS1893CY-10 Rev 1/07
The purpose of this bit is to allow an STA to determine if the ICS1893CY-10 detects a Jabber condition as
defined in the ISO/IEC specification.The ICS1893CY-10 Jabber Detection function is controlled by the
Jabber Inhibit bit in the 10Base-T Operations register (bit 18.5). To detect a Jabber condition, first the
ICS1893CY-10 Jabber Detection function must be enabled. When bit 18.5 is logic:
•
•
Note:
1. The Jabber Detect bit is accessible through both the Status register (as bit 1.1) and the QuickPoll
2. The Jabber Detect bit is a latching high (LH) bit. (For more information on latching high and latching low
The STA reads bit 1.0 to determine if the ICS1893CY-10 has an extended register set. In the
ICS1893CY-10 this bit is always logic one, indicating that it has extended registers.
Zero, the ICS1893CY-10 disables Jabber Detection and sets the Jabber Detect bit to logic zero.
One, the ICS1893CY-10 enables Jabber Detection and sets the Jabber Detect bit to logic one upon
detection of a Jabber condition. When no Jabber condition is detected, the Jabber Detect bit is not
altered.
Detailed Status Register (as bit 17.2). A read of either register clears the Jabber Detect bit.
bits, see
ICS1893CY-10 Data Sheet - Release
Section 7.1.4.1, “Latching High Bits”
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
68
and
Section 7.1.4.2, “Latching Low
Chapter 7 Management Register Set
Bits”.)