Si5369-EVB Silicon Laboratories Inc, Si5369-EVB Datasheet - Page 10

MCU, MPU & DSP Development Tools SI5369 DEV KIT

Si5369-EVB

Manufacturer Part Number
Si5369-EVB
Description
MCU, MPU & DSP Development Tools SI5369 DEV KIT
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of Si5369-EVB

Processor To Be Evaluated
Si5369
Interface Type
I2C, SPI
Operating Supply Voltage
3.3 V
Lead Free Status / Rohs Status
 Details
10
Table 4. AC Specifications
(V
Single-Ended Reference Clock Input Pin XA (XB with cap to GND)
Input Resistance
Input Voltage Swing
Differential Reference Clock Input Pins (XA/XB)
Input Voltage Swing
CKINn Input Pins
Input Frequency
Input Duty Cycle
(Minimum Pulse
Width)
Input Capacitance
Input Rise/Fall Time
CKOUTn Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency
(Output not config-
ured for CMOS or
Disabled)
Maximum Output
Frequency in CMOS
Format
Output Rise/Fall
(20–80 %) @
622.08 MHz output
Output Rise/Fall
(20–80%) @
212.5 MHz output
*Note: Input to output phase skew after an ICAL is not controlled and can assume any value.
DD
= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T
Parameter
XA/XB
CKO
CKO
Symbol
CKN
CKN
CKN
XA
XA
CKN
CKO
CKO
VPP
RIN
TRF
TRF
TRF
CIN
DC
VPP
F
F
F
Output not configured for
A
RATE[1:0] = LM, MH,
RATE[1:0] = LM, MH,
limitation applies only
RATE[1:0] = LM, MH
Whichever is smaller
= –40 to 85 °C)
(i.e., the 40% / 60%
CMOS or Disabled
to high frequency
Test Condition
CMOS Output
C
See Figure 2
See Figure 2
V
ac coupled
ac coupled
LOAD
Preliminary Rev. 0.4
20–80%
DD
clocks)
N1 = 5
N1 = 4
N1  6
= 1.71
= 5 pF
1.213
0.002
0.002
Min
970
0.5
0.5
40
2
Typ
230
12
212.5
1134
Max
710
945
350
1.2
2.4
1.4
60
11
3
8
MHz
MHz
MHz
MHz
Unit
GHz
V
V
k
pF
ns
ns
ps
ns
%
PP
PP

Related parts for Si5369-EVB