LFE2M70E-5FN900C Lattice, LFE2M70E-5FN900C Datasheet - Page 36

IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-900

LFE2M70E-5FN900C

Manufacturer Part Number
LFE2M70E-5FN900C
Description
IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-900
Manufacturer
Lattice
Series
LatticeECP2Mr
Datasheet

Specifications of LFE2M70E-5FN900C

No. Of Logic Blocks
67000
No. Of Macrocells
34000
No. Of Speed Grades
5
Total Ram Bits
4534Kbit
No. Of I/o's
416
Clock Management
DLL, PLL
I/o Supply Voltage
3.465V
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFE2M70E-5FN900C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 2-31. Output and Tristate Block for Left, Right and Bottom Edges
DQSXFER
DQSXFER
ONEG1
ONEG0
ONEG1
ONEG0
OPOS1
OPOS0
OPOS1
OPOS0
(CLKA)
(CLKB)
ECLK1
ECLK2
ECLK1
ECLK2
CLKA
CLKB
CLK1
CLK1
TD
TD
* Shared with input register
Clock Transfer
Clock Transfer
Registers
Registers
D
D
D-Type*
D-Type*
D-Type
D-Type
D
D
Tristate Logic
Tristate Logic
Q
Q
Q
Q
*
*
D
D
Latch
Latch
Q
Q
0
1
0
1
0
1
0
1
2-33
Note: Simplified version does not show CE and SET/RESET details
0
1
0
1
0
1
0
1
D
D
D
D
D
D
D
D
/LATCH
/LATCH
/LATCH
/LATCH
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
LatticeECP2/M Family Data Sheet
Q
Q
Q
Q
Q
Q
Q
Q
Comp PIO (B) in LVDS I/O Pair
True PIO (A) in LVDS I/O Pair
D
D
D
D
DDR Output
DDR Output
Latch
Latch
Latch
Latch
Registers
Registers
Q
Q
Q
Q
Output Logic
Output Logic
0
1
0
1
0
1
0
1
0
1
0
1
Programmable
Programmable
Control
Control
0
1
0
1
Architecture
0
1
0
1
DO
DO
TO
TO

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