MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 192

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

executed by the CPU. . The alternative is to always wait the amount of time equal to the appropriate number of cycles at the
slowest possible rate the clock could be running. This sub-section will describe the hardware handshake protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the
target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This
pulse is generated by the target MCU when a command, issued by the host, has been successfully executed (see
This pulse is referred to as the ACK pulse. After the ACK pulse has finished: the host can start the bit retrieval if the last issued
command was a read command, or start a new command if the last command was a write command or a control command
(BACKGROUND, GO, GO_UNTIL(171) or TRACE1). The ACK pulse is not issued earlier than 32 serial clock cycles after the
BDM command was issued. The end of the BDM command is assumed to be the 16th tick of the last bit. This minimum delay
assures enough time for the host to perceive the ACK pulse. Note also that, there is no upper limit for the delay between the
command and the related ACK pulse, since the command execution depends upon the CPU bus, which in some cases could be
very slow due to long accesses taking place.This protocol allows a great flexibility for the POD designers, since it does not rely
on any accurate time measurement or short response time to any event in the serial communication.
Figure 62
example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The
target BDM decodes the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE
operation. Having retrieved the data, the BDM issues an ACK pulse to the host controller, indicating that the addressed byte is
ready to be retrieved. After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form
of a word and the host needs to determine which is the appropriate byte based on whether the address was odd or even.
Freescale Semiconductor
BKGD Pin
(Target MCU)
BDM Clock
ACK Pulse
BKGD Pin
shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an
Transmits
Last Command Bit
16th Tick of the
Target
READ_BYTE
If the ACK pulse was issued by the target, the host assumes the previous command was
executed. If the CPU enters stop prior to executing a hardware command, the ACK pulse
will not be issued meaning that the BDM command was not executed. After entering stop
mode, the BDM command is no longer pending.
Host
High-Impedance
Byte Address
Figure 62. Handshake Protocol at the Command Level
Target
32 Cycles
Figure 61. Target Acknowledge Pulse (ACK)
BDM Decodes
the Command
MM912_634 Advance Information, Rev. 4.0
Minimum Delay
From the BDM Command
NOTE
16 Cycles
BDM Executes the
READ_BYTE Command
Speedup Pulse
Target
BDM Issues the
ACK Pulse (out of scale)
(2) Bytes are
Retrieved
Host
Next Bit
Earliest
Start of
High-Impedance
Host
Command
New BDM
Target
Figure
61).
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