MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 225

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

if the breakpoint happens to coincide with a SWI instruction in user code. On returning from BDM, the SWI from user code gets
executed.
BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is
attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code, checks the ENABLE
and returns if ENABLE is not set. If not serviced by the monitor then the breakpoint is re-asserted when the BDM returns to normal
CPU flow.
If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code could coincide with a
DBG breakpoint. The CPU ensures that BDM requests have a higher priority than SWI requests. Returning from the BDM/SWI
service routine care must be taken to avoid a repeated breakpoint at the same address.
Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows the BGND instruction
is the first instruction executed when normal program execution resumes.
4.32.5
4.32.5.1
Defining the state control registers as SCR1,SCR2, SCR3 and M0,M1,M2 as matches on channels 0,1,2 respectively. SCR
encoding supported by S12SDBGV1 are shown in black. SCR encoding supported only in S12SDBGV2 are shown in red. For
backwards compatibility the new scenarios use a 4th bit in each SCR register. Thus the existing encoding for SCRx[2:0] is not
changed.
4.32.5.2
A trigger is generated if a given sequence of 3 code events is executed.
Scenario 1 is possible with S12SDBGV1 SCR encoding
4.32.5.3
A trigger is generated if a given sequence of 2 code events is executed.
Freescale Semiconductor
DBGBRK
Application Information
X
State Machine scenarios
Scenario 1
Scenario 2
0
1
1
1
When program control returns from a tagged breakpoint using an RTI or BDM GO command
without program counter modification it returns to the instruction whose tag generated the
breakpoint. To avoid a repeated breakpoint at the same location reconfigure the DBG
module in the SWI routine, if configured for an SWI breakpoint, or over the BDM interface
by executing a TRACE command before the GO to increment the program flow past the
tagged instruction.
SCR1=0011
State1
(DBGC1[4])
BDM Bit
M1
X
0
X
1
1
Table 331. Breakpoint Mapping Summary
MM912_634 Advance Information, Rev. 4.0
SCR2=0010
State2
Figure 69. Scenario 1
Enabled
BDM
X
X
1
0
1
M2
NOTE
SCR3=0111
State3
Active
BDM
X
X
0
1
0
M0
Final State
Breakpoint to BDM
Breakpoint to SWI
Breakpoint to SWI
No Breakpoint
No Breakpoint
Breakpoint
Mapping
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