MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 247

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.38.3.2.7
This register controls the PLL functionality.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect.
Freescale Semiconductor
COPOSCSEL
0x003A
RTIOSCSEL
Reset
PLLSEL
W
R
PSTP
Field
PRE
PCE
7
6
3
2
1
0
PLL Select Bit
This bit selects the PLLCLK as source of the System Clocks (Core Clock and Bus Clock).
PLLSEL can only be set to 0, if UPOSC=1.
UPOSC= 0 sets the PLLSEL bit.
Entering Full Stop Mode sets the PLLSEL bit.
Pseudo Stop Bit
This bit controls the functionality of the oscillator during Stop Mode.
Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the resonator in
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE
RTI Enable During Pseudo Stop Bit — PRE enables the RTI during Pseudo Stop Mode.
Note: If PRE=0 or RTIOSCSEL=0 then the RTI will go static while Stop Mode is active. The RTI counter will not be reset.
COP Enable During Pseudo Stop Bit — PCE enables the COP during Pseudo Stop Mode.
Note: If PCE=0 or COPOSCSEL=0 then the COP will go static while Stop Mode is active. The COP counter will not be reset.
RTI Clock Select — RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the RTIOSCSEL
bit re-starts the RTI timeout period.
RTIOSCSEL can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the RTIOSCSEL bit.
COP Clock Select — COPOSCSEL selects the clock source to the COP. Either IRCCLK or OSCCLK. Changing the
COPOSCSEL bit re-starts the COP timeout period.
COPOSCSEL can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the COPOSCSEL bit.
7
0
0
S12CPMU PLL Control Register (CPMUPLL)
0
1
0
1
0
1
0
1
0
1
0
1
case of frequent STOP conditions at the expense of a slightly increased power consumption.
bit is already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator t
before entering Pseudo Stop Mode.
System clocks are derived from OSCCLK if oscillator is up (UPOSC=1, f
System clocks are derived from PLLCLK, f
Oscillator is disabled in Stop Mode (Full Stop Mode).
Oscillator continues to run in Stop Mode (Pseudo Stop Mode), option to run RTI and COP.
RTI stops running during Pseudo Stop Mode.
RTI continues running during Pseudo Stop Mode if RTIOSCSEL=1.
COP stops running during Pseudo Stop Mode
COP continues running during Pseudo Stop Mode if COPOSCSEL=1
RTI clock source is IRCCLK.
RTI clock source is OSCCLK.
COP clock source is IRCCLK.
COP clock source is OSCCLK
6
0
0
Table 349. S12CPMU PLL Control Register (CPMUPLL)
Table 348. CPMUCLKS Descriptions
FM1
MM912_634 Advance Information, Rev. 4.0
5
0
FM0
4
0
BUS
Description
= f
PLL
/ 2.
3
0
0
BUS
2
0
0
= f
OSC
/ 2.
1
0
0
0
0
0
UPOSC
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