MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 302

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.40.3.2.5
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the
CPU.
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not writable.
4.40.3.2.6
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
All assigned bits in the FERCNFG register are readable and writable.
Freescale Semiconductor
Reset
Reset
W
W
IGNSF
R
R
FDFD
FSFD
Field
CCIE
7
4
1
0
CCIE
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed.
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The FECCR registers
will not be updated during the Flash array read operation with FDFD set unless an actual double bit fault is detected.
Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations
and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The FECCR registers will not be
updated during the Flash array read operation with FSFD set unless an actual single bit fault is detected.
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read
7
0
7
0
0
Flash Configuration Register (FCNFG)
Flash Error Configuration Register (FERCNFG)
0
1
0
1
0
1
and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG register is set (see
Section
0
1
an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section
Command complete interrupt disabled
An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see
All single bit faults detected during array reads are reported
Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated
Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see
4.40.3.2.6)
4.40.3.2.6)
6
0
0
6
0
0
Table 420. Flash Error Configuration Register (FERCNFG)
= Unimplemented or Reserved
= Unimplemented or Reserved
Table 418. Flash Configuration Register (FCNFG)
Table 419. FCNFG Field Descriptions
MM912_634 Advance Information, Rev. 4.0
5
0
0
5
0
0
IGNSF
4
0
4
0
0
Description
3
0
0
3
0
0
2
0
0
2
0
0
Section
DFDIE
FDFD
1
0
1
0
Section
Section
4.40.3.2.7)
Section
4.40.3.2.7) and
4.40.3.2.8).
4.40.3.2.7)
SFDIE
FSFD
0
0
0
0
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