MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 202

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.32.3.2.3
Read: Anytime
Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed.
Freescale Semiconductor
Address: 0x0022
TSOURCE
Reset
TRCMOD
SSF[2:0]
TALIGN
W
R
Field
Field
TBF
2–0
3–2
7
6
0
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If
this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in
DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no
affect on this bit
This bit is also visible at DBGCNT[7]
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During a debug session
on each transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then
these bits retain their value to reflect the last state of the state sequencer before disarming. If a debug session is ended by an
internal event, then the state sequencer returns to state0 and these bits are cleared to indicate that state0 was entered during
the session. On arming the module the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See
Table 275
Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU system is
secured, this bit cannot be set and tracing is inhibited.
This bit must be set to read the trace buffer.
Trace Mode Bits — See
flow information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace memory are
inhibited. In Detail Mode, address and data for all memory and register accesses is stored. In Compressed Pure PC mode the
program counter value for each instruction executed is stored. See
Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session.
7
0
0
Debug Trace Control Register (DBGTCR)
0
1
0
1
Debug session without tracing requested
Debug session with tracing requested
Trigger at end of stored data
Trigger before storing data
.
TSOURCE
6
0
Table 275. SSF[2:0] — State Sequence Flag Bit Encoding
Table 276. Debug Trace Control Register (DBGTCR)
101,110,111
Section 4.32.4.5.2, “Trace Modes
SSF[2:0]
000
001
010
100
011
Table 277. DBGTCR Field Descriptions
Table 274. DBGSR Field Descriptions
MM912_634 Advance Information, Rev. 4.0
5
0
0
4
0
0
Description
Description
for detailed Trace Mode descriptions. In Normal Mode, change of
State0 (disarmed)
Current State
Final State
Reserved
Table
3
0
State1
State2
State3
TRCMOD
278.
2
0
1
0
0
TALIGN
0
0
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