MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 87

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.14.3.1
Note:
4.14.3.1.1
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1),
the associated PWM output is enabled immediately. However, the actual PWM waveform is not available on the associated PWM
output until its clock source begins its next cycle, due to the synchronization of PWMEx and the clock source.
4.14.3.1.2
The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit. If the polarity bit is one, the
PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the
polarity bit is zero, the output starts low and then goes high when the duty count is reached.
4.14.3.1.3
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described by the following.
Freescale Semiconductor
Offset
82.
Reset
PWME[1:0]
PPOL[1:0]
W
R
CAE[1:0]
PCLK1
PCLK0
Field
(82)
7–6
3–2
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
1-0
5
4
0x60
CAE1
PWM Control Register (PWMCTL)
7
0
Center Aligned Output Modes on Channels 1–0
Pulse Width Channel 1 Clock Select
Pulse Width Channel 0 Clock Select
Pulse Width Channel 1–0 Polarity Bits
Pulse Width Channel 1–0 Enable
PWM Enable (PWMEx)
The first PWM cycle after enabling the channel can be irregular. If both PWM channels are
disabled (PWME1–0 = 0), the prescaler counter shuts off for power savings.
PWM Polarity (PPOLx)
PPOLx register bits can be written anytime. If the polarity changes while a PWM signal is
being generated, a truncated or stretched pulse can occur during the transition
PWM Clock Select (PCLKx)
0
1
0
1
0
1
0
1
0
1
clock source begins its next cycle.
Channels 1–0 operate in left aligned output mode.
Channels 1–0 operate in center aligned output mode.
Clock B is the clock source for PWM channel 1.
Clock SB is the clock source for PWM channel 1.
Clock A is the clock source for PWM channel 0.
Clock SA is the clock source for PWM channel 0.
PWM channel 1–0 outputs are low at the beginning of the period, then go high when the duty count is reached.
PWM channel 1–0 outputs are high at the beginning of the period, then go low when the duty count is reached.
Pulse width channel 1–0 is disabled.
Pulse width channel 1–0 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its
CAE0
6
0
Table 120. PWMCTL - Register Field Descriptions
Table 119. PWM Control Register (PWMCTL)
PCLK1
MM912_634 Advance Information, Rev. 4.0
5
0
PCLK0
NOTE
NOTE
4
0
Description
PPOL1
3
0
PPOL0
2
0
PWM Control Module (PWM8B2C)
PWME1
1
0
Access: User read/write
PWME0
0
0
87