Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 121

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 63. PWM Fault Status Register (PWMFSTAT)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bit Position
[7]
RLDFlag
[6]
Reserved
[5]
DBGFLAG
[4:3]
Reserved
[2]
F1FLAG
[1]
C0FLAG
[0]
FFLAG
Note: For this register, W1C means you must write one to clear the flag.
PWM Fault Status Register
RLDFlag
R/W1C
U
7
The PWM fault status (PWMFSTAT) register provides status of fault inputs and timer
reload. The fault flags indicate the fault source, which is active. If a fault source is masked,
the flag in this register is not set when the source is asserted. The reload flag is set when
the timer compare values are updated. Clear flags by writing 1 to the flag bits. Fault flag
bits are cleared only if the associated fault source has deasserted.
Value (H)
0
0
Reserved DBGFLAG
R
6
0
Reload Flag
This bit is set and latched when a PWM timer reload occurs. Writing a 1
to this bit clears the flag.
Reserved
Always reads 0.
Debug Flag
This bit is set and latched when DEBUG mode is entered. Writing a
1 to this bit clears the flag.
Reserved
Always reads 0.
Fault1 Flag
This bit is set and latched when fault1 is asserted. Writing a 1
to this bit clears the flag.
Comparator 0 Flag
This bit is set and latched when comparator is asserted. Writing a
1 to this bit clears the flag.
Fault Flag
This bit is set and latched when the fault0 input is asserted. Writing a 1
Description
to this bit clears the flag.
R/W1C
U
5
P R E L I M I N A R Y
4
FF_E385H
Reserved
00
R
Z16FMC Series Motor Control MCUs
3
F1FLAG
R/W1C
U
2
Multi-Channel PWM Timer
Product Specification
C0FLAG
R/W1C
U
1
FFLAG
R/W1C
U
0
99