Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 200

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
ters accessing different Slaves) or during the data phase when the Masters are attempting
to write different data to the same Slave.
When a Master loses arbitration, software is informed by means of the Arbitration Lost
interrupt. Software repeats the same transaction again at a later time.
A special case occurs when a slave transaction starts just before software attempts to start
a new master transaction by setting the
slave states before the START bit is set and the I
address match occurs and the I
cleared and an Arbitration Lost interrupt is asserted. Software minimizes the chance of
this occurring by checking the BUSY bit in the I2CSTATE Register before initiating a
master transaction. If a slave address match does not occur, the Arbitration Lost interrupt
does not occur and the
transaction after the I
Master Address Only Transactions
It is sometimes appropriate to perform an address-only transaction to determine if a partic-
ular Slave device is able to respond. This transaction is performed by monitoring the
ACKV bit in the I2CSTATE Register after the address has been written to the I2CDATA
Register and the START bit has been set. After ACKV is set, the ACK bit in the
I2CSTATE Register determines if the Slave is able to communicate. The STOP bit must be
set in the I2CCTL Register to terminate the transaction without transferring data. For a 10-
bit slave address, if the first address byte is acknowledged, the second address byte must
also be sent to determine if the appropriate slave is responding.
Another approach is to set both the STOP and START bits (for sending a 7-bit address).
After both bits are cleared (7-bit address has been sent and transaction is complete), the
ACK
bit after the second TDRE interrupt (second address byte is being sent).
Master Transaction Diagrams
In the following transaction diagrams, shaded regions indicate data transferred from the
Master to the Slave and unshaded regions indicate data transferred from the Slave to the
Master. The transaction field labels are defined as:
S
W
A
A
P
bit is read to determine if the slave is acknowledged. For a 10-bit slave, set the STOP
Start
Write
Acknowledge
Not Acknowledge
Stop
2
C bus is no longer busy.
START
P R E L I M I N A R Y
bit is not cleared. The I
2
C Controller receives or transmits data, the
START
bit. In this case the state machine enters the
Z16FMC Series Motor Control MCUs
2
C Controller does not arbitrate. If a slave
2
C Controller initiates the master
I2C Master/Slave Controller
Product Specification
START
bit is
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