Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 302
![Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC32AG20SG
Manufacturer Part Number
Z16FMC32AG20SG
Description
Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC32AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC32AG20SG
Manufacturer:
Zilog
Quantity:
160
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Table 162. Trace Control Register (TRACECTL)
PS028702-1210
Bits
31
30
29
28
27:24
23:0
Bits
Field
RESET
R/W
ADDR
Bits
7
Trace Control Register
Description
PC – Break on Program Counter Match
This bit will enable the hardware breakpoint.
0 = Break on program counter match disabled.
1 = Break on program counter match enabled.
ST – Status
This bit is set when a hardware breakpoint occurs.
0 = No breakpoint occurred because this bit was last written to zero.
1 = Breakpoint has occurred or this bit written to one.
RD – Break on data read
This bit will enable the hardware watchpoint for data reads.
0 = Hardware watchpoint on read disabled.
1 = Hardware Watchpoint on read enabled.
WR – Break on data write
This bit will enable the hardware watchpoint for data writes.
0 = Hardware watchpoint on data write disabled.
1 = Hardware watchpoint on data write enabled.
MASK – Watchpoint address mask
The MASK field specifies the number of bits in ADDR to ignore when comparing against
addresses for read and write watchpoints. The mask is set to ignore 0 to 15 of the lower
address bits to allow the watchpoint to monitor a memory block up to 32K in size.
ADDR – Breakpoint Address
The address to match when generating a breakpoint.
Description
TRACEEN – Trace Enable
0 = Trace is disabled.
1 = Traces is enabled
TRACEEN
R/W
7
0
The Trace Control Register (TRACECTL) is used to enable the Trace operation. It also
selects the size of the trace buffer.
R
6
0
R
5
0
Reserved
P R E L I M I N A R Y
R
4
0
FF_E013
Z16FMC Series Motor Control MCUs
R
3
0
2
Product Specification
TRACESEL
R/W
000
On-Chip Debugger
1
0
280
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